Florent Kermarrec 9a50f6ece6 bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).		2020-11-06 14:44:36 +01:00
..
arty.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
common.py	bench/common: add s7_load_bios/s7_set_sys_clk functions.	2020-09-14 10:54:35 +02:00
ddr3_mr_gen.py	bench: add DDR3 Mode Register settings generator.	2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py	bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).	2020-11-06 14:44:36 +01:00
genesys2.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
kc705.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
kcu105.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
xcu1525.py	bench/xcu1525: use specific output_dir per channel (to allow // build of bitstreams for the different channels).	2020-11-06 10:47:26 +01:00