Florent Kermarrec b4c552a77f core/multiplexer: fix command steering for nphases=1 (SDRAM), thanks jfng		2019-01-17 09:06:09 +01:00
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core	core/multiplexer: fix command steering for nphases=1 (SDRAM), thanks jfng	2019-01-17 09:06:09 +01:00
frontend	frontend/ecc: add error injection capability	2019-01-04 10:43:51 +01:00
phy	phy/gensdrphy: make CAS latency configurable	2019-01-08 09:44:58 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: allow setting electrical settings with DDR4	2019-01-08 17:00:57 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: adjust MT48LC16M16 timings	2018-12-27 22:25:59 +01:00
sdram_init.py	sdram_init: generate ddrx_mr1 only if mr1 is not None	2019-01-07 22:59:20 +01:00