Florent Kermarrec c2a779df46 bench: Update test targets (add_csr no longer required).		2021-04-19 13:40:17 +02:00
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arty.py	bench: Update test targets (add_csr no longer required).	2021-04-19 13:40:17 +02:00
common.py	bench/common: Cleanup, Increase sys_clk measure time to 5s.	2021-03-12 14:29:43 +01:00
ddr3_mr_gen.py	bench: add DDR3 Mode Register settings generator.	2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py	bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).	2020-11-06 14:44:36 +01:00
genesys2.py	bench: Update test targets (add_csr no longer required).	2021-04-19 13:40:17 +02:00
kc705.py	bench: Update test targets (add_csr no longer required).	2021-04-19 13:40:17 +02:00
kcu105.py	bench: Update test targets (add_csr no longer required).	2021-04-19 13:40:17 +02:00
xcu1525.py	bench: Update test targets (add_csr no longer required).	2021-04-19 13:40:17 +02:00