This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litedram
mirror of
https://github.com/enjoy-digital/litedram.git
Watch
1
Star
0
Fork
You've already forked litedram
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
efd7a47890
litedram
/
test
History
Florent Kermarrec
849b1f6c35
frontend/axi: generate rlast signal
2018-09-06 11:11:17 +02:00
..
__init__.py
update code, start bankmachine refactoring and remove old code (will be rewritten)
2015-09-15 10:22:39 +02:00
common.py
test: update
2018-09-06 11:10:45 +02:00
test_axi.py
frontend/axi: generate rlast signal
2018-09-06 11:11:17 +02:00
test_bist.py
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00
test_downconverter.py
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00
test_upconverter.py
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00