Florent Kermarrec 79806aad20 modules/ddr3: add MT41K64M16		2019-02-20 22:47:55 +01:00
..
core	core/crossbar: cosmetic	2019-01-22 13:56:35 +01:00
frontend	frontend/bist: fix for data_width < 31 (16 bits SDRAMs)	2019-01-18 17:56:32 +01:00
phy	phy/s7ddrphy and usddrphy: add cmd_latency parameter	2019-02-19 18:00:23 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: allow setting electrical settings with DDR4	2019-01-08 17:00:57 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules/ddr3: add MT41K64M16	2019-02-20 22:47:55 +01:00
sdram_init.py	litedram/sdram_init/ddr4: disable data mask (not required)	2019-02-12 10:52:39 +01:00