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Merge pull request #71 from antonblanchard/gen_tx_rx_slots 

liteeth/gen: Allow configuration of nrxslots and ntxslots
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enjoy-digital 2021-08-06 14:58:53 +02:00 committed by GitHub
parent 947ed03720 7ac3fe681a
commit 2a8cac96ba
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1 changed files with 8 additions and 2 deletions
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liteeth/gen.py
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@ -213,14 +213,20 @@ class MACCore(PHYCore):
# PHY -------------------------------------------------------------------------------------- # PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config) PHYCore.__init__(self, platform, core_config)
nrxslots = core_config.get("nrxslots", 2)
ntxslots = core_config.get("ntxslots", 2)
mac_memsize = (nrxslots + ntxslots) * buffer_depth
# MAC -------------------------------------------------------------------------------------- # MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC( self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy, phy = self.ethphy,
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
endianness = core_config["endianness"]) endianness = core_config["endianness"],
nrxslots = nrxslots,
ntxslots = ntxslots)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
self.add_csr("ethmac") self.add_csr("ethmac")
# Wishbone Interface ----------------------------------------------------------------------- # Wishbone Interface -----------------------------------------------------------------------