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phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer

This commit is contained in:
Florent Kermarrec 2016-02-24 23:51:31 +01:00
parent 1dae2b802c
commit 5583fe5543
1 changed files with 2 additions and 2 deletions
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4
liteeth/phy/s6rgmii.py
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@ -152,8 +152,8 @@ class LiteEthPHYRGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads), "eth_tx") self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads), "eth_rx") self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source
if hasattr(pads, "mdc"): if hasattr(pads, "mdc"):