liteeth_gen: Add initial (and wip) etherbone support.

This commit is contained in:
Florent Kermarrec 2023-06-08 22:04:18 +02:00
parent f00d95c534
commit 7f4df17615
1 changed files with 15 additions and 0 deletions

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@ -47,6 +47,8 @@ from liteeth import phy as liteeth_phys
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
@ -306,6 +308,19 @@ class UDPCore(PHYCore):
with_sys_datapath = (data_width == 32), with_sys_datapath = (data_width == 32),
) )
# Etherbone --------------------------------------------------------------------------------
# /!\ WIP /!\
with_etherbone = True
if with_etherbone:
assert (data_width == 32)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys")
axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
platform.add_extension(axil_bus.get_ios("mmap"))
self.submodules += axi.Wishbone2AXILite(self.etherbone.wishbone.bus, axil_bus)
self.comb += axil_bus.connect_to_pads(platform.request("mmap"), mode="master")
# /!\ WIP /!\
# UDP Ports -------------------------------------------------------------------------------- # UDP Ports --------------------------------------------------------------------------------
for name, port in core_config["udp_ports"].items(): for name, port in core_config["udp_ports"].items():
# Parameters. # Parameters.