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Merge pull request #28 from jersey99/phy-usrgmii 

Changes to get usrgmii and s7rgmii working in hardware
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enjoy-digital 2020-01-28 08:54:09 +01:00 committed by GitHub
parent 3a54bf2b8b 8ecaaf0546
commit 8a4f38339a
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 4 additions and 4 deletions
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2
liteeth/phy/s7rgmii.py
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@ -118,7 +118,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
from litex.soc.cores.clock import S7PLL
self.submodules.pll = pll = S7PLL()
pll.register_clkin(ClockSignal("eth_rx"), 125e6)
pll.create_clkout(self.cd_eth_tx, 125e6)
pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase)
eth_tx_clk_obuf = Signal()

6
liteeth/phy/usrgmii.py
View File

@ -77,7 +77,7 @@ class LiteEthPHYRGMIIRX(Module):
i_CNTVALUEIN=0,
i_IDATAIN=rx_ctl_ibuf,
i_RST=0,
i_EN_VTC=0,
i_EN_VTC=1,
o_DATAOUT=rx_ctl_idelay),
Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
@ -110,7 +110,7 @@ class LiteEthPHYRGMIIRX(Module):
i_CNTVALUEIN=0,
i_IDATAIN=rx_data_ibuf[i],
i_RST=0,
i_EN_VTC=0,
i_EN_VTC=1,
o_DATAOUT=rx_data_idelay[i]),
Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
@ -159,7 +159,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
from litex.soc.cores.clock import USPLL
self.submodules.pll = pll = USPLL()
pll.register_clkin(ClockSignal("eth_rx"), 125e6)
pll.create_clkout(self.cd_eth_tx, 125e6)
pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase)
eth_tx_clk_obuf = Signal()