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core/mac: use fifo_depth of 64 for all phys

This commit is contained in:
Florent Kermarrec 2016-03-15 19:41:53 +01:00
parent 32243934fb
commit c3e15e7f7b
1 changed files with 2 additions and 8 deletions
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10
liteeth/core/mac/core/__init__.py
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@ -1,8 +1,6 @@
from liteeth.common import * from liteeth.common import *
from liteeth.core.mac.core import gap, preamble, crc, padding, last_be from liteeth.core.mac.core import gap, preamble, crc, padding, last_be
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
from liteeth.phy.mii import LiteEthPHYMII
from liteeth.phy.rmii import LiteEthPHYRMII
class LiteEthMACCore(Module, AutoCSR): class LiteEthMACCore(Module, AutoCSR):
@ -82,12 +80,8 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline += [rx_converter] rx_pipeline += [rx_converter]
# Cross Domain Crossing # Cross Domain Crossing
if isinstance(phy, (LiteEthPHYMII, LiteEthPHYRMII)): tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
fifo_depth = 8 rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
else:
fifo_depth = 64
tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc) self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc) self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)