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mac: Rename sys_datapath to with_sys_datapath.

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This commit is contained in:
Florent Kermarrec 2021-10-05 10:23:01 +02:00
parent a00a200547
commit ce8523f31b
2 changed files with 5 additions and 5 deletions
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4
liteeth/mac/__init__.py
View file

@ -21,13 +21,13 @@ class LiteEthMAC(Module, AutoCSR):
hw_mac = None,
timestamp = None,
full_memory_we = False,
sys_data_path = False):
with_sys_datapath = False):
assert dw%8 == 0
assert interface in ["crossbar", "wishbone", "hybrid"]
assert endianness in ["big", "little"]
self.submodules.core = LiteEthMACCore(phy, dw, with_preamble_crc, sys_data_path)
self.submodules.core = LiteEthMACCore(phy, dw, with_preamble_crc, with_sys_datapath)
self.csrs = []
if interface == "crossbar":
self.submodules.crossbar = LiteEthMACCrossbar(dw)

6
liteeth/mac/core.py
View file

@ -19,8 +19,8 @@ from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SI
class LiteEthMACCore(Module, AutoCSR):
def __init__(self, phy, dw,
with_sys_datapath = False,
with_preamble_crc = True,
sys_data_path = True,
with_padding = True):
core_dw = dw
@ -30,7 +30,7 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline = [phy]
tx_pipeline = [phy]
if sys_data_path:
if with_sys_datapath:
self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
cd_tx = cd_rx = "sys"
dw = core_dw
@ -93,7 +93,7 @@ class LiteEthMACCore(Module, AutoCSR):
tx_pipeline += [padding_inserter]
rx_pipeline += [padding_checker]
if not sys_data_path:
if not with_sys_datapath:
self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
# Graph