Xiretza 6a9a5132f6 Update gen.py to work with latest LiteX in wishbone mode ... Previously, it would fail with: $ liteeth/gen.py examples/wishbone_mii.yml [snip] Traceback (most recent call last): File "liteeth/gen.py", line 346, in <module> main() File "liteeth/gen.py", line 331, in main soc = MACCore(platform, core_config) File "liteeth/gen.py", line 244, in __init__ self.add_wb_master(bridge.wishbone) File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master self.bus.add_master(master=wbm) File "[...]/litex/soc/integration/soc.py", line 347, in add_master master = self.add_adapter(name, master, "m2s") File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter bridge_cls = { KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)		2020-08-22 11:00:42 +02:00
..
core	core/mac: add missing separators, fix typos.	2020-06-19 19:59:53 +02:00
frontend	frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).	2020-07-13 10:08:50 +02:00
mac	mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43).	2020-07-13 11:27:25 +02:00
phy	phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work).	2020-05-29 10:39:18 +02:00
software	liteeth/software: remove libwip/libuip examples.	2019-06-17 21:17:52 +02:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	common: remove Port.connect and use 2 separate Record.connect.	2020-06-22 14:36:44 +02:00
crossbar.py	core/mac: add missing separators, fix typos.	2020-06-19 19:59:53 +02:00
gen.py	Update gen.py to work with latest LiteX in wishbone mode	2020-08-22 11:00:42 +02:00