Florent Kermarrec 0feed1720d phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). ... This makes clocking more flexible and allows routing on more boards (ex: Pano Logic G2). Since TX clocking does not need clock phase relationship with the input clock using a combinatorial path is fine.		2020-05-29 10:39:18 +02:00
..
__init__.py	phy/__init__: import all phys.	2020-03-01 20:13:23 +01:00
a7_1000basex.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
a7_gtp.py	phy/1000basex: cleanup primitive instances, use Open signal class on open ports, polish code comments	2020-01-28 10:43:08 +01:00
common.py	phy/common: use CSRField for MDIO registers	2020-01-28 10:43:33 +01:00
ecp5rgmii.py	phy/ecp5rgmii: review/simplify inband_status integration.	2020-05-19 09:41:09 +02:00
gmii.py	phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work).	2020-05-29 10:39:18 +02:00
gmii_mii.py	litex.build: update from migen.genlib.io litex.build.io.	2020-04-10 09:20:41 +02:00
k7_1000basex.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
ku_1000basex.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
mii.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
model.py	phy: cleanup imports/dw	2020-01-17 23:19:56 +01:00
pcs_1000basex.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-24 11:43:10 +02:00
rmii.py	litex.build: update from migen.genlib.io litex.build.io.	2020-04-10 09:20:41 +02:00
s6rgmii.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
s7rgmii.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00
usrgmii.py	phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).	2020-03-01 19:10:39 +01:00