litescope/test/test_analyzer.py

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#
# This file is part of LiteScope.
#
# Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litescope import LiteScopeAnalyzer
class TestAnalyzer(unittest.TestCase):
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def test_analyzer(self):
def generator(dut):
dut.data = []
# Configure Trigger
yield from dut.analyzer.trigger.mem_value.write(0x0010)
yield from dut.analyzer.trigger.mem_mask.write(0xffff)
yield from dut.analyzer.trigger.mem_write.write(1)
# Configure Subsampler
yield from dut.analyzer.subsampler.value.write(2)
# Configure Storage
yield from dut.analyzer.storage.length.write(256)
yield from dut.analyzer.storage.offset.write(8)
yield from dut.analyzer.storage.enable.write(1)
yield
for i in range(16):
yield
# Wait capture
while not (yield from dut.analyzer.storage.done.read()):
yield
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# Read captured datas
while (yield from dut.analyzer.storage.mem_level.read()) > 0:
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dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
yield
class DUT(Module):
def __init__(self):
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counter = Signal(32)
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self.sync += counter.eq(counter + 1)
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
dut = DUT()
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generators = {"sys" : [generator(dut)]}
clocks = {"sys": 10, "scope": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
self.assertEqual(dut.data, [524 + 3*i for i in range(len(dut.data))])