global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
This commit is contained in:
Florent Kermarrec
parent
7af786e47e
commit
8f88088f63
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@ -13,9 +13,9 @@ class LiteScopeTermUnit(Module):
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# # #
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self.comb += [
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source.stb.eq(sink.stb),
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source.valid.eq(sink.valid),
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source.hit.eq((sink.data & self.mask) == self.trig),
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sink.ack.eq(source.ack)
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sink.ready.eq(source.ready)
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]
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@ -45,9 +45,9 @@ class LiteScopeRangeDetectorUnit(Module):
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# # #
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self.comb += [
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source.stb.eq(sink.stb),
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source.valid.eq(sink.valid),
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source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)),
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sink.ack.eq(source.ack)
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sink.ready.eq(source.ready)
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]
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@ -90,8 +90,8 @@ class LiteScopeEdgeDetectorUnit(Module):
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self.comb += both.eq(self.both_mask & (rising | falling))
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self.comb += [
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source.stb.eq(sink.stb & self.buffer.q.stb),
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self.buffer.q.ack.eq(source.ack),
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source.valid.eq(sink.valid & self.buffer.q.valid),
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self.buffer.q.ready.eq(source.ready),
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source.hit.eq((rising | falling | both) != 0)
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]
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@ -24,9 +24,9 @@ class LiteScopeSubSamplerUnit(Module):
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self.comb += [
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done.eq(counter >= self.value),
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sink.connect(source),
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source.stb.eq(sink.stb & done),
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counter_ce.eq(source.ack),
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counter_reset.eq(source.stb & source.ack & done)
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source.valid.eq(sink.valid & done),
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counter_ce.eq(source.ready),
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counter_reset.eq(source.valid & source.ready & done)
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]
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@ -69,7 +69,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
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change = Signal()
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self.comb += change.eq(
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sink.stb &
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sink.valid &
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(sink.data != buf.source.data)
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)
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@ -77,23 +77,23 @@ class LiteScopeRunLengthEncoderUnit(Module):
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fsm.act("BYPASS",
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buf.source.connect(source),
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counter_reset.eq(1),
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If(sink.stb & ~change,
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If(sink.valid & ~change,
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If(self.enable,
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NextState("COUNT")
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)
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)
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)
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fsm.act("COUNT",
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buf.source.ack.eq(1),
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counter_ce.eq(sink.stb),
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buf.source.ready.eq(1),
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counter_ce.eq(sink.valid),
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If(~self.enable,
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NextState("BYPASS")
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).Elif(change | counter_done,
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source.stb.eq(1),
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source.valid.eq(1),
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source.data[:len(counter)].eq(counter),
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source.data[-1].eq(1), # Set RLE bit
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buf.source.ack.eq(source.ack),
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If(source.ack,
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buf.source.ready.eq(source.ready),
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If(source.ready,
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NextState("BYPASS")
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)
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)
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@ -136,7 +136,7 @@ class LiteScopeRecorderUnit(Module):
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += [
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self.source.stb.eq(fifo.source.stb),
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self.source.valid.eq(fifo.source.valid),
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self.source.data.eq(fifo.source.data)
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]
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fsm.act("IDLE",
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@ -145,31 +145,31 @@ class LiteScopeRecorderUnit(Module):
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NextState("PRE_HIT_RECORDING"),
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fifo.reset.eq(1),
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),
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fifo.source.ack.eq(self.source.ack)
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fifo.source.ready.eq(self.source.ready)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.sink.stb.eq(data_sink.stb),
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fifo.sink.valid.eq(data_sink.valid),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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data_sink.ready.eq(fifo.sink.ready),
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fifo.source.ack.eq(fifo.level >= self.offset),
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If(trigger_sink.stb & trigger_sink.hit,
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fifo.source.ready.eq(fifo.level >= self.offset),
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If(trigger_sink.valid & trigger_sink.hit,
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NextState("POST_HIT_RECORDING")
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)
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)
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fsm.act("POST_HIT_RECORDING",
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self.post_hit.eq(1),
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If(self.qualifier,
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fifo.sink.stb.eq(trigger_sink.stb &
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fifo.sink.valid.eq(trigger_sink.valid &
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trigger_sink.hit &
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data_sink.stb)
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data_sink.valid)
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).Else(
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fifo.sink.stb.eq(data_sink.stb)
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fifo.sink.valid.eq(data_sink.valid)
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),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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data_sink.ready.eq(fifo.sink.ready),
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If(~fifo.sink.ack | (fifo.level >= self.length),
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If(~fifo.sink.ready | (fifo.level >= self.length),
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NextState("IDLE")
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)
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)
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@ -185,8 +185,8 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
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self._offset = CSRStorage(bits_for(depth))
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self._done = CSRStatus()
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self._source_stb = CSRStatus()
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self._source_ack = CSR()
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self._source_valid = CSRStatus()
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self._source_ready = CSR()
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self._source_data = CSRStatus(dw)
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# # #
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@ -198,7 +198,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
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self.offset.eq(self._offset.storage),
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self._done.status.eq(self.done),
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self._source_stb.status.eq(self.source.stb),
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self._source_valid.status.eq(self.source.valid),
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self._source_data.status.eq(self.source.data),
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self.source.ack.eq(self._source_ack.re)
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self.source.ready.eq(self._source_ready.re)
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]
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@ -33,11 +33,11 @@ class LiteScopeSumUnit(Module, AutoCSR):
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# drive source
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self.comb += [
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source.stb.eq(reduce(and_, [sink.stb for sink in sinks])),
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source.valid.eq(reduce(and_, [sink.valid for sink in sinks])),
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source.hit.eq(lut.dat_r)
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]
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for i, sink in enumerate(sinks):
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self.comb += sink.ack.eq(sink.stb & source.ack)
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self.comb += sink.ready.eq(sink.valid & source.ready)
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class LiteScopeSum(LiteScopeSumUnit, AutoCSR):
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@ -70,11 +70,11 @@ class LiteScopeTrigger(Module, AutoCSR):
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def do_finalize(self):
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self.submodules.sum = LiteScopeSum(len(self.ports))
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for i, port in enumerate(self.ports):
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# Note: port's ack is not used and supposed to be always 1
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# Note: port's ready is not used and supposed to be always 1
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self.comb += [
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port.sink.stb.eq(self.sink.stb),
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port.sink.valid.eq(self.sink.valid),
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port.sink.data.eq(self.sink.data),
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self.sink.ack.eq(1),
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self.sink.ready.eq(1),
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port.source.connect(self.sum.sinks[i])
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]
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self.comb += self.sum.source.connect(self.source)
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@ -25,7 +25,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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self.sink = stream.Endpoint(data_layout(self.dw))
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self.comb += [
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self.sink.stb.eq(1),
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self.sink.valid.eq(1),
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self.sink.data.eq(self.data)
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]
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@ -55,7 +55,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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# connect trigger
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self.comb += [
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self.trigger.sink.stb.eq(sink.stb),
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self.trigger.sink.valid.eq(sink.valid),
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self.trigger.sink.data.eq(sink.data),
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]
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@ -113,9 +113,9 @@ class LiteScopeLogicAnalyzerDriver():
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def upload(self):
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if self.debug:
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print("uploading")
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while self.recorder_source_stb.read():
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while self.recorder_source_valid.read():
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self.data.append(self.recorder_source_data.read())
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self.recorder_source_ack.write(1)
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self.recorder_source_ready.write(1)
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if self.with_rle:
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if self.rle_enable.read():
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self.data = self.data.decode_rle()
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