8299105b7f
vcd: creates gtkw file if filter_*.txt file is present
2022-06-20 14:51:45 +02:00
878f21a647
CONTRIBUTORS: Updpte.
2022-05-02 13:49:48 +02:00
2fc04386d3
examples/arty: Use full import.
2022-05-02 13:34:19 +02:00
d1c480d0e8
litescope/core: Remove duplicates from split_signals.
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Still allow the user to add duplicated signals, but will not error when running Litescope in --gui mode.
2022-04-15 09:16:24 +02:00
f1acdf4c17
litescope_gui: Add initial and very simple GUI support.
2022-03-16 16:56:07 +01:00
1d85cbcb6d
core/_Storage: Simplify using connect and create specific endpoint for read_source.
2022-03-14 11:45:58 +01:00
3fb1018737
test/test_analzer: Update.
2022-03-14 10:21:57 +01:00
13813457d7
core/_Storage: Simplify/Fix w_conv.sink.data assignement.
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- Constant(0, pads_bits) breaks cases where pads_bits==0.
- Assignement of MSBs to 0 is implicit.
2022-03-14 09:53:54 +01:00
df23b3f8cd
Merge pull request #41 from smunaut/proto
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core: Change upload protocol to allow bursting through xBone
2022-03-14 09:33:06 +01:00
c5137773f6
core: Change upload protocol to allow bursting through xBone
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Instead of using a very wide CSR, we force it to max 32 bits
and read each captured words as several sub-words.
Also, instead of checking for 'valid' flag every time, we
just read the 'level' of the memory buffer. Given the way
LiteScope works, we know capture is done and this is how many
words there is to read.
All in all this means that reading the data off the
buffer is just reading the same address over and over meaning
we can use very long bursts which helps _a_lot_ to speed things
up.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-09 22:07:27 +01:00
6f0287fecd
core: Fix default samplerate and convert to int.
2022-03-07 17:39:31 +01:00
71187f8bd0
Merge pull request #40 from jevinskie/jev/vcd-timescale-fix
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VCD: Add samplerate support to fix displayed timestamps
2022-01-31 16:55:12 +01:00
21f6fcaa28
VCD: Add samplerate support to fix displayed timestamps
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To use this, pass the samplerate kwarg to LiteScopeAnalyzer(). If using the sys domain, soc_obj.sys_clk_freq works.
2022-01-29 13:44:27 -08:00
42a357714b
ci: Install ninja-build/meson.
2022-01-05 09:24:43 +01:00
769b9b6e61
Bump year.
2022-01-05 09:07:13 +01:00
08072a78ba
Copyrights: Bump year.
2021-08-31 17:48:07 +02:00
14e8af8dd9
CONTRIBUTORS: Update.
2021-08-31 17:47:36 +02:00
45f562d63c
core/LiteScopeAnalyzer: Switch register parameter to boolean.
2021-08-25 14:09:53 +02:00
1596bff127
Merge pull request #30 from antmicro/jboc/registered-inputs
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litescope/core: add option to register input signals to cut timings
2021-08-25 13:23:59 +02:00
405b912829
Merge pull request #31 from sthornington/master
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Fix the cli error messages to make it clearer when you need to provide more CSVs
2021-08-25 13:17:15 +02:00
bf1c37864a
Merge branch 'master' into master
2021-08-25 13:17:08 +02:00
ea431069f7
Merge pull request #36 from DurandA/clear-scope
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litescope/core: add function to clear scope
2021-08-25 13:16:43 +02:00
431c730874
software/dump/json: Fix typo.
2021-08-25 13:06:00 +02:00
9437f52233
Merge pull request #35 from DurandA/json-exporter
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software/dump: add JSON dump
2021-08-25 13:05:20 +02:00
1243ab3c81
software/dump: add JSON dump
2021-05-24 03:57:58 +02:00
fab60ab5e0
litescope/core: add function to clear scope
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The analyzer driver can be reused for further capturing by calling
the clear() function.
2021-05-24 03:57:03 +02:00
72c9930705
test/test_examples: Update.
2021-05-03 12:12:16 +02:00
fe515d43e8
fix test, broken by the vendor_ prefixing of the platform artifacts
2021-04-10 19:04:38 -04:00
1e5305a2a4
trivial change
2021-04-10 18:58:42 -04:00
53637af809
fix typo
2021-04-10 13:59:27 -04:00
ad2a781681
fix value conversion for hex values
2021-04-10 13:58:32 -04:00
2f37678b61
optional parameter to pass in the SoC CSR CSV, in addition to the analyzer CSV, necessary if the SoC was build with a --csr-csv other than csr.csv. Also improve the error messages a bit.
2021-04-10 13:07:14 -04:00
824985cdd3
litescope/core: add option to register input signals to cut timings
2021-03-23 09:58:52 +01:00
f7a9672284
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:14:45 +01:00
f78400aa29
ci: install RISC-V GCC.
2020-12-17 16:56:31 +01:00
c8b7e1a922
litescope/core: set default csr_csv to csr_csv="analyzer.csv".
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Simplify creating basic analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [...]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, depth=512)
self.add_csr("analyzer")
2020-11-30 15:04:09 +01:00
0a67448ce9
ci: migrate from Travis CI to Github Actions.
2020-11-24 13:55:54 +01:00
94e2d15c94
software/litescope_cli: cleanup, use --csv to select analyzer file and add --dump argument.
2020-10-30 11:58:38 +01:00
e6e5675100
software/litescope_cli: add name support (default="analyzer").
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We can have several analyzers in the design, this allows selecting the one to use.
2020-10-23 10:31:46 +02:00
d6911390c0
software/litescope_cli: add group support.
2020-10-16 10:40:24 +02:00
dc9109030a
software/driver/analyzer/add_trigger: add support for binary/hexa expressions with x support.
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ex: litescope_cli -v sig1 0b111x0
ex: litescope_cli -v sig2 0x1234567x
2020-09-03 13:16:32 +02:00
69de7c4930
software/Dump: add add_scope_clk and add_scope_trig methods and add scope_clk/trig to dumps.
2020-09-03 09:23:19 +02:00
219a90122f
core/Trigger: also apply mask to trigger value (avoid having doing it in software).
2020-09-02 17:09:25 +02:00
12be70325e
software/litescope_cli: set default length to None (do a capture with max depth).
2020-09-02 10:55:32 +02:00
bd10138124
core/_Storage: fix size of length/offset signals.
2020-09-02 10:54:38 +02:00
02b543e5ba
litescope_cli: add capture subsampling support.
2020-08-25 09:28:15 +02:00
2739d5a069
add SPDX License identifier to header and specify file is part of LiteScope.
2020-08-23 16:45:20 +02:00
ec7bd6b47d
getting started: update.
2020-08-07 23:10:29 +02:00
7d227740bd
Merge pull request #27 from cklarhorst/fix-storage-wrong-clock-domain
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Fix: 2 signals in the storage class belong to the wrong clock domain
2020-08-07 14:20:14 +02:00
ad4e46c8c6
Fix: 2 signals in the storage class belong to the wrong clock domain
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Signals & Domain overview:
- self.{offset,length}.storage belong to sys clock
- offset, length belong to scope clock
- mem belongs to scope clock
Therefore, everything that involves mem needs to use offset/length
2020-08-07 13:56:06 +02:00
Franck Jullien
Florent Kermarrec
Sylvain Munaut
Jevin Sweval
Arnaud Durand
Simon Thornington
Jędrzej Boczar
Christian Klarhorst