e6e5675100
software/litescope_cli: add name support (default="analyzer").
...
We can have several analyzers in the design, this allows selecting the one to use.
2020-10-23 10:31:46 +02:00
d6911390c0
software/litescope_cli: add group support.
2020-10-16 10:40:24 +02:00
dc9109030a
software/driver/analyzer/add_trigger: add support for binary/hexa expressions with x support.
...
ex: litescope_cli -v sig1 0b111x0
ex: litescope_cli -v sig2 0x1234567x
2020-09-03 13:16:32 +02:00
69de7c4930
software/Dump: add add_scope_clk and add_scope_trig methods and add scope_clk/trig to dumps.
2020-09-03 09:23:19 +02:00
219a90122f
core/Trigger: also apply mask to trigger value (avoid having doing it in software).
2020-09-02 17:09:25 +02:00
12be70325e
software/litescope_cli: set default length to None (do a capture with max depth).
2020-09-02 10:55:32 +02:00
bd10138124
core/_Storage: fix size of length/offset signals.
2020-09-02 10:54:38 +02:00
02b543e5ba
litescope_cli: add capture subsampling support.
2020-08-25 09:28:15 +02:00
2739d5a069
add SPDX License identifier to header and specify file is part of LiteScope.
2020-08-23 16:45:20 +02:00
ad4e46c8c6
Fix: 2 signals in the storage class belong to the wrong clock domain
...
Signals & Domain overview:
- self.{offset,length}.storage belong to sys clock
- offset, length belong to scope clock
- mem belongs to scope clock
Therefore, everything that involves mem needs to use offset/length
2020-08-07 13:56:06 +02:00
16e65556a2
Fix: A WaitTimer belongs to the wrong clock domain (trigger flush)
...
The WaitTimer for the trigger flush should belong to the scope clock
instead of the sys clock
2020-08-05 16:21:08 +02:00
bc6c5e35ee
examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer.
2020-08-05 13:22:29 +02:00
0182377a07
examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script.
2020-08-05 12:41:50 +02:00
e07bdbfb29
software/dump/sigrok: Support width > 1.
2020-02-26 18:23:45 +01:00
bcd883ef8e
README: update
2019-11-22 19:47:46 +01:00
1f09678653
core: remove cd parameter retro-compatibility
2019-11-22 19:42:52 +01:00
c1b52f1887
core: cosmetic
2019-11-22 19:42:04 +01:00
bbc98b4404
core: remove reset on scope clk
2019-11-22 19:34:07 +01:00
7a9fa9d3b1
core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet)
2019-09-24 18:03:06 +02:00
284253d558
core: add csr_csv parameter and export csv_csv on do_exit
2019-09-10 12:38:34 +02:00
9e3b9d84ce
add CONTRIBUTORS file and add copyright header to all files.
2019-06-24 10:04:55 +02:00
7f4dc390d9
Add functionality to flatten values that are sampled using a serdes.
...
This code add some functionality to flatten the values back from
the serial to parallel conversion that happens when sampling
using the serdes.
2019-06-14 16:57:33 +02:00
2474ce9db2
software/dump/common: change variable name for values2x loop (thanks keesj)
2019-05-28 12:42:48 +02:00
c1d8bdf6f2
core: fix Trigger flush when disabled
2018-12-28 10:38:23 +01:00
4f8b9a3567
analyzer-driver: use default depth from config
...
The configuration already knows what the default depth is, so just use
the default depth from there.
Also set the default offset to 0, since that is frequently a good default.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-13 13:48:09 +08:00
3567b68981
dump/vcd: fix code generation
2018-08-30 14:39:09 +02:00
182b683586
core: change cd parameter to clock_domain (keep retro compatibility for now)
2018-08-28 11:58:44 +02:00
71ffaa7484
add trigger depth option
2018-08-02 11:01:44 +08:00
bfd06f819e
core: add FSM support (and example)
2018-07-20 09:36:42 +02:00
f03345d9f0
software/driver/analyzer: add get_instant_value to get instant value of one signal
2018-06-08 09:07:06 +02:00
af5bfd131f
software/driver/analyzer: add assertions
2018-06-04 10:10:03 +02:00
d919f90cf6
core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals)
2018-05-31 09:32:22 +02:00
2233bc290e
core: another cleanup/simplify pass
2018-05-28 23:12:15 +02:00
a269e67a10
software: add rising/falling edge support
2018-05-28 19:42:46 +02:00
65b7f08cbc
core: add full flag for trigger memory
2018-05-28 19:41:44 +02:00
c0bab06765
core: add sequential-triggering and simplify control
2018-05-28 19:16:53 +02:00
8d4c1ddcf9
core: simplify and run storage in "scope" clock domain to get rid of cd_ratio.
2018-05-28 18:05:05 +02:00
9d5e605df3
replace litex.gen imports with migen imports
2018-02-23 13:43:47 +01:00
985585f0b9
__init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports
2018-02-19 14:50:03 +01:00
72e71e7200
core: simplify
2018-01-20 12:43:16 +01:00
7757727f5b
implement memory flush in hardware instead of software
2017-11-17 15:11:03 +01:00
d4d63d7474
software/driver/analyzer: fix groups build
2017-07-24 22:57:19 +02:00
8d87992b95
litescope/software/dump/sigrok: remove 8 bits limitation and some cleanup
2017-06-23 11:40:44 +02:00
d8649fca5f
software/dump/sigrok: add limitation to 8 bits, will be fixed later
2017-06-23 10:50:08 +02:00
2048acf80e
software/dump/sigrok: fix write_data, now working :)
2017-06-23 08:57:10 +02:00
3d35e72a48
software/driver/analyzer: fix wait_done
2017-06-22 19:24:08 +02:00
dff7ac8d4e
software/dump/sigrok: rename capture file to dump
2017-06-22 19:20:34 +02:00
92710208de
software/driver/analyzer: add wait_done method
2017-06-22 19:11:11 +02:00
0c4d0f4505
software/dump/sigrok: fix samplerate generation (2x since we are doubling data to show capture clk)
2017-06-22 18:45:15 +02:00
f8ea15363c
software/dump/common: rename clk to capture_clk in dumps
2017-06-22 18:41:08 +02:00
Florent Kermarrec
Christian Klarhorst
Vegard Storheil Eriksen
kees.jongenburger
Sean Cross
bunnie