litex-boards/litex_boards/targets/trenz_max1000.py

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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
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# Copyright (c) 2019-2021 Antti Lukats <antti.lukats@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex_boards.platforms import trenz_max1000
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from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import M12L64322A
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
# Clk / Rst
clk12 = platform.request("clk12")
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-C8")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk12, 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = trenz_max1000.Platform()
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# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
# Reduce SRAM size.
kwargs["integrated_sram_size"] = 0x1000
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on CYC1000", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"), # Winbond W9864G6JT
l2_cache_size = kwargs.get("l2_size", 0)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MAX1000")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.build:
builder.build()
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if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
main()