2020-08-23 09:00:17 -04:00
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
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2023-04-10 23:23:33 -04:00
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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2020-08-23 09:00:17 -04:00
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# SPDX-License-Identifier: BSD-2-Clause
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2020-01-13 08:21:54 -05:00
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from litex.build.generic_platform import *
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2022-11-05 03:07:14 -04:00
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from litex.build.xilinx import Xilinx7SeriesPlatform
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2020-05-05 03:42:34 -04:00
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from litex.build.openocd import OpenOCD
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2020-01-13 08:21:54 -05:00
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("AB11"), IOStandard("LVDS")),
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Subsignal("n", Pins("AC11"), IOStandard("LVDS"))
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),
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2020-11-03 04:48:41 -05:00
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("cpu_reset_n", 0, Pins("G9"), IOStandard("LVCMOS25")),
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# Leds
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("user_led", 0, Pins("U9"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 1, Pins("V12"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 2, Pins("V13"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 3, Pins("W13"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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2022-05-19 03:14:32 -04:00
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# The Serial which connects to the second UART
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# of the FTDI on the base board (first FTDI port is JTAG)
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("serial", 0,
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Subsignal("tx", Pins("A20")),
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Subsignal("rx", Pins("B20")),
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IOStandard("LVCMOS15")
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),
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# Serial This one is multiplexed with the I2C bus
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("serial", 1,
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Subsignal("tx", Pins("W11")),
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Subsignal("rx", Pins("AB16")),
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IOStandard("LVCMOS15")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AE11 AF9 AD10 AB10 AA9 AB9 AA8 AC8",
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"AA7 AE8 AF10 AD8 AE10 AF8 AC7"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AD11 AA10 AF12"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AE13"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE12"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA12"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("Y12"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"Y3 U5 AD4 AC4 AF19 AC16 AB19 V14"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AA2 Y2 AB2 V1 Y1 W1 AC2 V2",
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"W3 V3 U1 U7 U6 V4 V6 U2",
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"AE3 AE6 AF3 AD1 AE1 AE2 AF2 AE5",
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"AD5 Y5 AC6 Y6 AB4 AD6 AB6 AC3",
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"AD16 AE17 AF15 AF20 AD15 AF14 AE15 AF17",
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"AA14 AA15 AC14 AD14 AB14 AB15 AA17 AA18",
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"AB20 AD19 AC19 AA20 AA19 AC17 AD18 AB17",
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"W15 W16 W14 V16 V19 V17 V18 Y17"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AB1 W6 AF5 AA5 AE18 Y15 AD20 W18"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("dqs_n", Pins("AC1 W5 AF4 AB5 AF18 Y16 AE20 W19"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("clk_p", Pins("AB12"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AC12"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AA13"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AD13"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15"), Misc("SLEW=SLOW")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH"),
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),
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# Don't use, this is for documentation only.
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# This pin sets DDR3 voltage. LOW = 1.3V, HI-Z = 1.5V, HIGH = illegal
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("ddram_vsel", 0, Pins('AA3'), IOStandard("SSTL15"), Misc("SLEW=SLOW")),
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]
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2023-04-10 03:06:42 -04:00
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_connectors = [
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("A", {
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15 : "W20", 16 : "AA23",
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17 : "Y21", 18 : "AB24",
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19 : "AD21",
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21 : "AE21", 22 : "AB21",
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24 : "AC21",
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25 : "AE22",
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27 : "AF22", 28 : "AB22",
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30 : "AC22",
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31 : "V21",
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33 : "W21", 34 : "AE23",
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36 : "AF23",
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37 : "V23",
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39 : "V24", 40 : "AF24",
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42 : "AF25",
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43 : "U24",
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45 : "U25", 46 : "Y22",
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48 : "AA22",
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49 : "AC23",
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51 : "AC24", 52 : "AD25",
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54 : "AE25",
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55 : "W25",
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57 : "W26", 58 : "AD23",
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60 : "AD24",
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61 : "U26",
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63 : "V26", 64 : "U22",
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66 : "V22",
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67 : "AB26",
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69 : "AC26", 70 : "W23",
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72 : "W24",
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73 : "AA25",
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75 : "AB25", 76 : "AD26",
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78 : "AE26",
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79 : "U21",
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81 : "Y20", 82 : "Y25",
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84 : "Y26",
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85 : "Y23",
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87 : "AA24", 88 : "D23",
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90 : "D24",
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91 : "C21", 92 : "E21",
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93 : "B21", 94 : "E22",
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95 : "D26",
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97 : "C26", 98 : "D21",
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100 : "C22",
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101 : "A23",
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103 : "A24", 104 : "F22",
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105 : "B20", 106 : "E23",
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107 : "A20",
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}),
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("B", {
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1 : "D6" ,
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3 : "D5" , 4: "H6",
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5 : "F6" , 6: "H5",
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7 : "F5" ,
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10: "K6",
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12: "K5",
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13 : "P2" ,
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16: "R4",
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17 : "P1" ,
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20: "R3",
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21 : "M2" ,
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24: "N4",
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25 : "M1" ,
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28: "N3",
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29 : "K2" ,
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32: "L4",
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33 : "K1" ,
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36: "L3",
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37 : "H2" ,
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40: "J4",
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41 : "H1" ,
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44: "J3",
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45 : "F2" ,
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47 : "F1" , 48: "G4",
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50: "G3",
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51 : "D2" ,
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53 : "D1" , 54: "E4",
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56: "E3",
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57 : "G11",
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59 : "F10", 60: "C4",
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62: "C3",
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63 : "B2" ,
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65 : "B1" , 66: "B6",
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68: "B5",
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69 : "A4" ,
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71 : "A3" , 72: "F19",
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74: "E20",
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75 : "C14",
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77 : "C13", 78: "H17",
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80: "H18",
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81 : "D14",
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83 : "D13", 84: "G19",
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86: "F20",
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87 : "J13",
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89 : "H13", 90: "L19",
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91 : "F14", 92: "L20",
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93 : "F13", 94: "K20",
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96: "J20",
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97 : "E13",
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99 : "E12", 100: "M17",
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101 : "G12", 102: "L18",
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103 : "F12", 104: "L17",
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106: "K18",
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107 : "J11",
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109 : "J10", 110: "K16",
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111 : "H12", 112: "K17",
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113 : "H11", 114: "J18",
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116: "J19",
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117 : "G10",
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119 : "G9" , 120: "H19",
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122: "G20",
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123 : "E11", 124: "D19",
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125 : "D11", 126: "D20",
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129 : "A13", 130: "G17",
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131 : "A12", 132: "F18",
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133 : "B10",
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135 : "A10", 136: "C17",
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138: "C18",
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139 : "B12",
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141 : "B11", 142: "C16",
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144: "B16",
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145 : "H14",
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147 : "G14", 148: "B17",
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150: "A17",
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151 : "C12",
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153 : "C11", 154: "E18",
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156: "D18",
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157 : "B14",
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159 : "A14", 160: "C19",
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162: "B19",
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163 : "B15", 164: "A18",
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165 : "A15", 166: "A19",
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}),
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("C", {
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69: "J8",
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71: "J14", 72 : "K15",
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74 : "M16",
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75: "A9",
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77: "A8", 78 : "G15",
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79: "C9", 80 : "F15",
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81: "B9", 82 : "J15",
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84 : "J16",
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85: "D9",
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87: "D8", 88 : "F17",
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89: "E10", 90 : "E17",
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91: "D10", 92 : "E15",
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94 : "E16",
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95: "F9",
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97: "F8", 98 : "H16",
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99: "H9", 100 : "G16",
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101: "H8", 102 : "D15",
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104 : "D16",
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105: "N18",
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107: "M19", 108 : "P16",
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109: "R16", 110 : "N17",
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111: "R17", 112 : "U17",
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114 : "T17",
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115: "P23",
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117: "N23", 118 : "R18",
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119: "T24", 120 : "P18",
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121: "T25", 122 : "R22",
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124 : "R23",
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125: "N19",
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127: "M20", 128 : "P24",
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129: "T18", 130 : "N24",
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131: "T19", 132 : "P19",
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134 : "P20",
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135: "U19",
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137: "U20", 138 : "T22",
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139: "T20", 140 : "T23",
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141: "R20", 142 : "K25",
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144 : "K26",
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145: "R25",
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147: "P25", 148 : "N21",
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150 : "N22",
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151: "R21",
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153: "P21", 154 : "M24",
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156 : "L24",
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157: "M21", 160 : "M25",
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159: "M22", 162 : "L25",
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161: "R26", 164 : "N26",
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163: "P26", 166 : "M26",
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2023-04-10 03:06:42 -04:00
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})
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]
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2020-01-13 08:21:54 -05:00
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# Platform -----------------------------------------------------------------------------------------
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2022-11-05 03:07:14 -04:00
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class Platform(Xilinx7SeriesPlatform):
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2020-01-13 11:22:33 -05:00
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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2020-01-13 08:21:54 -05:00
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2022-02-14 05:35:08 -05:00
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7k160tffg676-2", _io, _connectors, toolchain=toolchain)
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2022-05-19 03:14:32 -04:00
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property CFGBVS GND [current_design]")
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# DDR3 is connected to banks 32, 33 and 34
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 32]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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# The VRP/VRN resistors are connected to bank 34.
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# Banks 32 and 33 have LEDs in the places, so we have to use the reference from bank 34
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# Bank 33 has no _T_DCI signals connected
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self.add_platform_command("set_property DCI_CASCADE {{32}} [get_iobanks 34]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]")
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# Important! Do not remove this constraint!
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# This property ensures that all unused pins are set to high impedance.
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# If the constraint is removed, all unused pins have to be set to HiZ in the top level file
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# This causes DDR3 to use 1.5V by default
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]")
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2020-01-13 08:21:54 -05:00
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2023-04-10 23:19:03 -04:00
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def add_baseboard(self, bb):
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self.add_connector(bb.connectors)
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2023-04-10 23:58:52 -04:00
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self.add_extension(bb.io)
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2023-04-10 18:39:11 -04:00
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2020-01-13 08:21:54 -05:00
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def create_programmer(self):
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2020-05-06 10:14:51 -04:00
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
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2020-05-05 05:45:41 -04:00
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def do_finalize(self, fragment):
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2022-11-05 03:07:14 -04:00
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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2022-05-19 17:42:06 -04:00
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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