2019-06-24 06:38:58 -04:00
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#!/usr/bin/env python3
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2020-08-23 09:00:17 -04:00
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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2019-06-24 06:38:58 -04:00
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2020-05-05 09:11:38 -04:00
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import os
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2019-06-24 06:38:58 -04:00
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import argparse
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import importlib
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from migen import *
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2020-04-10 04:26:19 -04:00
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from litex.build.io import CRG
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2019-06-24 06:38:58 -04:00
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy import LiteEthPHY
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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2020-03-21 13:29:52 -04:00
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def __init__(self, platform, with_ethernet=False, **kwargs):
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2019-06-24 06:38:58 -04:00
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sys_clk_freq = int(1e9/platform.default_clk_period)
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2019-12-03 03:07:09 -05:00
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# SoCCore ----------------------------------------------------------------------------------
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2020-06-30 12:11:04 -04:00
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX Simple SoC",
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ident_version = True,
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**kwargs)
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2020-01-16 04:28:09 -05:00
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2019-12-03 03:07:09 -05:00
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# CRG --------------------------------------------------------------------------------------
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2019-06-24 06:38:58 -04:00
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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2020-01-16 04:28:09 -05:00
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# Ethernet ---------------------------------------------------------------------------------
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2020-03-21 13:29:52 -04:00
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHY(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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clk_freq = self.clk_freq)
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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2019-06-24 06:38:58 -04:00
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Generic LiteX SoC")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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2019-06-24 06:38:58 -04:00
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builder_args(parser)
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soc_core_args(parser)
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2020-05-05 09:11:38 -04:00
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("platform", help="Module name of the platform to build for")
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2020-06-02 07:45:05 -04:00
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parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build")
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args = parser.parse_args()
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platform_module = importlib.import_module(args.platform)
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2020-06-02 07:45:05 -04:00
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if args.toolchain is not None:
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platform = platform_module.Platform(toolchain=args.toolchain)
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else:
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platform = platform_module.Platform()
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soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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2019-06-24 06:38:58 -04:00
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if __name__ == "__main__":
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main()
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