targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args

litex_boards/community/targets/ac701.py

@@ -51,10 +51,7 @@ class BaseSoC(SoCSDRAM):
         platform = ac701.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/community/targets/de10lite.py

@@ -85,9 +85,7 @@ class BaseSoC(SoCSDRAM):
         platform = de10lite.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)

litex_boards/community/targets/de1soc.py

@@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM):
         platform = de1soc.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)

litex_boards/community/targets/de2_115.py

@@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM):
         platform = de2_115.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)
@@ -86,7 +84,6 @@ class BaseSoC(SoCSDRAM):
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
-            # ISSI IS42S16320D-7TL
             sdram_module = IS42S16320(self.clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
                 geom_settings   = sdram_module.geom_settings,

litex_boards/community/targets/ecp5_evn.py

@@ -45,9 +45,7 @@ class BaseSoC(SoCCore):
         platform = ecp5_evn.Platform(toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         crg = _CRG(platform, sys_clk_freq, x5_clk_freq)

litex_boards/community/targets/pipistrello.py

@@ -147,15 +147,12 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, **kwargs):
         sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
         platform     = pipistrello.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/official/targets/arty.py

@@ -48,14 +48,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = arty.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -81,7 +78,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
                                                self.platform.request("eth"))

litex_boards/official/targets/de0nano.py

@@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM):
         platform = de0nano.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)

litex_boards/official/targets/genesys2.py

@@ -41,14 +41,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = genesys2.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -72,7 +69,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))

litex_boards/official/targets/kc705.py

@@ -43,14 +43,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = kc705.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -76,7 +73,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
                                             self.platform.request("eth"), clk_freq=self.clk_freq)

litex_boards/official/targets/kcu105.py

@@ -77,14 +77,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = kcu105.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -111,7 +108,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
         self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,

litex_boards/official/targets/minispartan6.py

@@ -49,9 +49,7 @@ class BaseSoC(SoCSDRAM):
         platform = minispartan6.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/official/targets/nexys4ddr.py

@@ -45,14 +45,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys4ddr.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))

litex_boards/official/targets/nexys_video.py

@@ -45,14 +45,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys_video.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))

litex_boards/official/targets/simple.py

@@ -19,14 +19,11 @@ from liteeth.mac import LiteEthMAC
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, platform, **kwargs):
         sys_clk_freq = int(1e9/platform.default_clk_period)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=integrated_rom_size,
-            integrated_main_ram_size=16*1024,
-            **kwargs)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
@@ -38,7 +35,7 @@ class EthernetSoC(BaseSoC):
     }
     mem_map.update(BaseSoC.mem_map)
 
-    def __init__(self, platform, integrated_rom_size=0x10000, **kwargs):
+    def __init__(self, platform, **kwargs):
         BaseSoC.__init__(self, platform, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),

litex_boards/official/targets/versa_ecp5.py

@@ -72,13 +72,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=integrated_rom_size,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -105,7 +103,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, toolchain="diamond", **kwargs):
-        BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(
             self.platform.request("eth_clocks"),

litex_boards/partner/targets/aller.py

@@ -59,8 +59,6 @@ class AllerSoC(SoCSDRAM):
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, sys_clk_freq,
             csr_data_width           = 32,
-            integrated_rom_size      = 0x10000,
-            integrated_sram_size     = 0x10000,
             integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
             ident                    = "Aller LiteX Test SoC", ident_version=True,
             with_uart=not with_pcie_uart)

litex_boards/partner/targets/c10lprefkit.py

@@ -94,9 +94,7 @@ class BaseSoC(SoCSDRAM):
         platform = c10lprefkit.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)

litex_boards/partner/targets/camlink_4k.py

@@ -71,9 +71,7 @@ class BaseSoC(SoCSDRAM):
         sys_clk_freq = int(81e6)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/partner/targets/hadbadge.py

@@ -52,9 +52,7 @@ class BaseSoC(SoCSDRAM):
         platform = hadbadge.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/partner/targets/nereid.py

@@ -59,8 +59,6 @@ class NereidSoC(SoCSDRAM):
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, sys_clk_freq,
             csr_data_width           = 32,
-            integrated_rom_size      = 0x10000,
-            integrated_sram_size     = 0x10000,
             integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
             ident                    = "Nereid LiteX Test SoC", ident_version=True,
             with_uart                = not with_pcie_uart)

litex_boards/partner/targets/netv2.py

@@ -50,14 +50,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = netv2.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -83,7 +80,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))

litex_boards/partner/targets/orangecrab.py

@@ -75,13 +75,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", **kwargs):
         platform = orangecrab.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=integrated_rom_size,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/partner/targets/tagus.py

@@ -61,8 +61,6 @@ class TagusSoC(SoCSDRAM):
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, sys_clk_freq,
             csr_data_width           = 32,
-            integrated_rom_size      = 0x10000,
-            integrated_sram_size     = 0x10000,
             integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
             ident                    = "Tagus LiteX Test SoC", ident_version=True,
             with_uart                = not with_pcie_uart)

litex_boards/partner/targets/trellisboard.py

@@ -79,13 +79,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
         platform = trellisboard.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=integrated_rom_size,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -111,7 +109,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, toolchain="diamond", **kwargs):
-        BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(
             self.platform.request("eth_clocks"),

litex_boards/partner/targets/ulx3s.py

@@ -55,9 +55,7 @@ class BaseSoC(SoCSDRAM):
 
         platform = ulx3s.Platform(device=device, toolchain=toolchain)
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-            integrated_rom_size=0x8000,
-            **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)