hadbadge: fix _CRG
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15f3457aea
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beccf670e5
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@ -40,7 +40,7 @@ class _CRG(Module):
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pll.register_clkin(clk8, 8e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked)
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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