Updated comment, added link to clocking documentation.

2020-05-25 14:48:24 -07:00 · 2020-05-25 14:48:24 -07:00 · 0648c04158
parent 1ab46562bd
commit 0648c04158
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/platforms/pano_logic_g2.py
+++ b/litex_boards/platforms/pano_logic_g2.py
@ -98,6 +98,7 @@ _io = [
        Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
    ),
    # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
+    # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
    ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),

 ]