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Updated comment, added link to clocking documentation.

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Skip Hansen 2020-05-25 14:48:24 -07:00
parent 1ab46562bd
commit 0648c04158
1 changed files with 1 additions and 0 deletions
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litex_boards/platforms/pano_logic_g2.py
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@ -98,6 +98,7 @@ _io = [
Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
), ),
# Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active) # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
# See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")), ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
] ]