antmicro_datacenter: add 1 cycle of latency for RCD IC

2025-01-03 03:43:36 -05:00 · 2022-01-26 15:57:34 +01:00 · 2022-01-26 15:57:34 +01:00 · 0b80890119
commit 0b80890119
parent d6fddc746f
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@ -75,6 +75,7 @@ class BaseSoC(SoCCore):
                memtype         = "DDR4",
                iodelay_clk_freq = iodelay_clk_freq,
                sys_clk_freq     = sys_clk_freq,
+                cmd_latency      = 1,
                is_rdimm         = True,
            )
            self.add_sdram("sdram",