partner: rename orange_crab to orangecrab
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@ -8,7 +8,7 @@ import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import orange_crab
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from litex_boards.platforms import orangecrab
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -76,7 +76,7 @@ class _CRG(Module):
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
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platform = orange_crab.Platform(toolchain=toolchain)
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platform = orangecrab.Platform(toolchain=toolchain)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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