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orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset. 

Allows the USB-ACM link to stay up during reset.
This commit is contained in:
Florent Kermarrec 2021-01-04 09:04:54 +01:00
parent 06cb49af37
commit 1fb24d4c71
1 changed files with 4 additions and 4 deletions
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8
litex_boards/targets/orangecrab.py
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@ -60,12 +60,12 @@ class _CRG(Module):
self.clock_domains.cd_usb_48 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL() usb_pll = ECP5PLL()
self.submodules += usb_pll self.submodules += usb_pll
self.comb += usb_pll.reset.eq(~por_done | ~rst_n | self.rst) self.comb += usb_pll.reset.eq(~por_done)
usb_pll.register_clkin(clk48, 48e6) usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6) usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootlooader) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(sys_clk_freq) reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n) self.comb += reset_timer.wait.eq(~rst_n)
@ -130,12 +130,12 @@ class _CRGSDRAM(Module):
self.clock_domains.cd_usb_48 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL() usb_pll = ECP5PLL()
self.submodules += usb_pll self.submodules += usb_pll
self.comb += usb_pll.reset.eq(~por_done | ~rst_n) self.comb += usb_pll.reset.eq(~por_done)
usb_pll.register_clkin(clk48, 48e6) usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6) usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootlooader) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(sys_clk_freq) reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n) self.comb += reset_timer.wait.eq(~rst_n)