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targets/xilinx_zc706: typo ZCU -> ZC

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Gwenhael Goavec-Merou 2024-03-30 11:54:28 +01:00
parent a72f2a2e68
commit 2392473b89
1 changed files with 1 additions and 1 deletions
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litex_boards/targets/xilinx_zc706.py
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@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZC706", **kwargs)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
#if not self.integrated_main_ram_size: #if not self.integrated_main_ram_size: