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targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).

This commit is contained in:
Florent Kermarrec 2022-03-22 17:32:35 +01:00
parent 9d452b0d74
commit 2a206def0f
10 changed files with 19 additions and 28 deletions
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2
litex_boards/targets/camlink_4k.py
View File

@ -29,7 +29,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #

5
litex_boards/targets/fpc_iii.py
View File

@ -31,7 +31,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.stop = Signal()
@ -70,8 +70,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------

5
litex_boards/targets/gsd_butterstick.py
View File

@ -38,7 +38,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -74,8 +74,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------

5
litex_boards/targets/gsd_orangecrab.py
View File

@ -78,7 +78,7 @@ class _CRGSDRAM(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -120,8 +120,7 @@ class _CRGSDRAM(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# USB PLL

5
litex_boards/targets/lambdaconcept_ecpix5.py
View File

@ -33,7 +33,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -69,8 +69,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset | self.rst),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset | self.rst),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------

5
litex_boards/targets/lattice_ecp5_vip.py
View File

@ -32,7 +32,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -67,8 +67,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# HDMI

5
litex_boards/targets/lattice_versa_ecp5.py
View File

@ -32,7 +32,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -68,8 +68,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------

5
litex_boards/targets/logicbone.py
View File

@ -33,7 +33,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -73,8 +73,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# USB PLL

5
litex_boards/targets/rcs_arctic_tern_bmc_card.py
View File

@ -35,7 +35,7 @@ class _CRG(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
self.clock_domains.cd_dvo = ClockDomain(reset_less=True)
@ -83,8 +83,7 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# Generate DVO clock

5
litex_boards/targets/trellisboard.py
View File

@ -60,7 +60,7 @@ class _CRGSDRAM(Module):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
@ -102,8 +102,7 @@ class _CRGSDRAM(Module):
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
self.comb += platform.request("dram_vtt_en").eq(1)