targets: Update LiteXArgumentParser imports.

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -121,7 +121,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=adi_adrv2crr_fmc.Platform, description="LiteX SoC on ADI ADRV2CRR-FMC")
     parser.add_target_argument("--sys-clk-freq",    default=150e6,       help="System clock frequency (default: 150 MHz)")
     parser.add_target_argument("--with-pcie",       action="store_true", help="Enable PCIe support")

litex_boards/targets/adi_plutosdr.py

@@ -76,7 +76,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=adi_plutosdr.Platform, description="LiteX SoC on Pluto SDR")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
 

litex_boards/targets/alchitry_au.py

@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=alchitry_au.Platform, description="LiteX SoC on Alchitry Au(+)")
     parser.add_target_argument("--flash",           action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--variant",         default="au",        help="Board variant (au or au+).")

litex_boards/targets/alchitry_mojo.py

@@ -143,7 +143,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=alchitry_mojo.Platform, description="LiteX SoC on Alchitry Mojo")
     parser.add_target_argument("--sys-clk-freq",           default=62.5e6,      help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",             default="1:1",       help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/aliexpress_xc7k420t.py

@@ -62,7 +62,7 @@ class BaseSoC(SoCCore):
 
 # Build --------------------------------------------------------------------------------------------  
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=aliexpress_xc7k420t.Platform, description="LiteX SoC on AliExpress u420t")
     parser.add_target_argument("--sys-clk-freq",   default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.")

litex_boards/targets/alinx_ax7010.py

@@ -56,7 +56,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=alinx_ax7010.Platform, description="LiteX SoC on zynq xc7z010")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency (default: 100MHz)")
     args = parser.parse_args()

litex_boards/targets/alinx_axu2cga.py

@@ -172,7 +172,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=alinx_axu2cga.Platform, description="LiteX SoC on Alinx AXU2CGA")
     parser.add_target_argument("--cable",        default="ft232",     help="JTAG interface.")
     parser.add_target_argument("--sys-clk-freq", default=25e6,        help="System clock frequency.")

litex_boards/targets/antmicro_artix_dc_scm.py

@@ -113,7 +113,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=antmicro_artix_dc_scm.Platform, description="LiteX SoC on Artix DC-SCM")
     parser.add_target_argument("--flash",                  action="store_true", help="Flash bitstream")
     parser.add_target_argument("--sys-clk-freq",           default=100e6,       help="System clock frequency.")

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -178,7 +178,7 @@ class LiteDRAMSettingsEncoder(json.JSONEncoder):
         return super().default(o)
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=antmicro_datacenter_ddr4_test_board.Platform, description="LiteX SoC on DDR4 Datacenter Test Board")
     parser.add_target_argument("--flash",                  action="store_true",    help="Flash bitstream")
     parser.add_target_argument("--sys-clk-freq",           default=100e6,           help="System clock frequency")

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -112,7 +112,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=antmicro_lpddr4_test_board.Platform, description="LiteX SoC on LPDDR4 Test Board")
     parser.add_target_argument("--flash",            action="store_true",    help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",     default=50e6,           help="System clock frequency.")

litex_boards/targets/berkeleylab_marble.py

@@ -145,7 +145,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=berkeleylab_marble.Platform, description="LiteX SoC on BerkeleyLab Marble")
     parser.add_target_argument("--sys-clk-freq",   default=125e6,       help="System clock frequency.")
     parser.add_target_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support.")

litex_boards/targets/camlink_4k.py

@@ -101,7 +101,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=camlink_4k.Platform, description="LiteX SoC on Cam Link 4K")
     parser.add_target_argument("--sys-clk-freq", default=81e6,        help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/colorlight_5a_75x.py

@@ -178,7 +178,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=colorlight_5a_75b.Platform, description="LiteX SoC on Colorlight 5A-75X")
     parser.add_target_argument("--board",             default="5a-75b",                 help="Board type (5a-75b or 5a-75e).")
     parser.add_target_argument("--revision",          default="7.0", type=str,          help="Board revision (6.0, 6.1, 7.0 or 8.0).")

litex_boards/targets/colorlight_i5.py

@@ -175,7 +175,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=colorlight_i5.Platform, description="LiteX SoC on Colorlight I5")
     parser.add_target_argument("--board",            default="i5",             help="Board type (i5).")
     parser.add_target_argument("--revision",         default="7.0", type=str,  help="Board revision (7.0).")

litex_boards/targets/decklink_intensity_pro_4k.py

@@ -61,7 +61,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=decklink_intensity_pro_4k.Platform, description="LiteX SoC Blackmagic Decklink Intensity Pro 4K")
     parser.add_target_argument("--sys-clk-freq", default=125e6,       help="System clock frequency.")
     parser.add_target_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")

litex_boards/targets/decklink_mini_4k.py

@@ -148,7 +148,7 @@ class BaseSoC(SoCMini):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=decklink_mini_4k.Platform, description="LiteX SoC Blackmagic Decklink Mini 4K")
     parser.add_target_argument("--sys-clk-freq",           default=148.5e6,     help="System clock frequency.")
     pcieopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -106,7 +106,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=decklink_quad_hdmi_recorder.Platform, description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
     parser.add_target_argument("--sys-clk-freq", default=200e6,       help="System clock frequency.")
     parser.add_target_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")

litex_boards/targets/digilent_arty.py

@@ -154,7 +154,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_arty.Platform, description="LiteX SoC on Arty A7")
     parser.add_target_argument("--flash",               action="store_true",              help="Flash bitstream.")
     parser.add_target_argument("--variant",             default="a7-35",                  help="Board variant (a7-35 or a7-100).")

litex_boards/targets/digilent_arty_s7.py

@@ -85,7 +85,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_arty_s7.Platform, description="LiteX SoC on Arty S7")
     parser.add_target_argument("--variant",        default="s7-50",     help="Board variant (s7-50 or s7-25).")
     parser.add_target_argument("--sys-clk-freq",   default=100e6,       help="System clock frequency.")

litex_boards/targets/digilent_arty_z7.py

@@ -155,7 +155,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_arty_z7.Platform, description="LiteX SoC on Arty Z7")
     parser.add_target_argument("--variant",      default="z7-20",     help="Board variant (z7-20 or z7-10).")
     parser.add_target_argument("--sys-clk-freq", default=125e6,       help="System clock frequency.")

litex_boards/targets/digilent_atlys.py

@@ -205,7 +205,7 @@ NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_atlys.Platform, description="LiteX SoC on Atlys")
     parser.add_target_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support.")
     parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")

litex_boards/targets/digilent_basys3.py

@@ -62,7 +62,7 @@ class BaseSoC(SoCCore):
 
 # Build --------------------------------------------------------------------------------------------  
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_basys3.Platform, description="LiteX SoC on Basys3")
     parser.add_target_argument("--sys-clk-freq",        default=75e6,        help="System clock frequency.")
     sdopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/digilent_cmod_a7.py

@@ -135,7 +135,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_cmod_a7.Platform, description="LiteX SoC on CMOD A7")
     parser.add_target_argument("--flash",        action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--variant",      default="a7-35",     help="Board variant (a7-35 or a7-100).")

litex_boards/targets/digilent_genesys2.py

@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_genesys2.Platform, description="LiteX SoC on Genesys2")
     parser.add_target_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/digilent_nexys4.py

@@ -205,7 +205,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_nexys4.Platform, description="LiteX SoC on Nexys4")
     parser.add_target_argument("--sys-clk-freq",           default=75e6,        help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/digilent_nexys4ddr.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_nexys4ddr.Platform, description="LiteX SoC on Nexys4DDR")
     parser.add_target_argument("--sys-clk-freq",           default=75e6,        help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/digilent_nexys_video.py

@@ -160,7 +160,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_nexys_video.Platform, description="LiteX SoC on Nexys Video")
     parser.add_target_argument("--sys-clk-freq",           default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-ethernet",          action="store_true", help="Enable Ethernet support.")

litex_boards/targets/digilent_pynq_z1.py

@@ -98,7 +98,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_pynq_z1.Platform, description="LiteX SoC on PYNQ Z1")
     parser.add_target_argument("--sys-clk-freq",        default=125e6,       help="System clock frequency.")
     parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")

litex_boards/targets/digilent_zedboard.py

@@ -145,7 +145,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_zedboard.Platform, description="LiteX SoC on Zedboard")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     parser.set_defaults(cpu_type="zynq7000")

litex_boards/targets/ebaz4205.py

@@ -65,7 +65,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=ebaz4205.Platform, description="LiteX SoC on EBAZ4205")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/efinix_t8f81_dev_kit.py

@@ -82,7 +82,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_t8f81_dev_kit.Platform, description="LiteX SoC on Efinix T8F81C Dev Kit")
     parser.add_target_argument("--flash", action="store_true",           help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",      default=33.333e6,  help="System clock frequency.")

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -118,7 +118,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_titanium_ti60_f225_dev_kit.Platform, description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit")
     parser.add_target_argument("--flash",          action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",   default=200e6,       help="System clock frequency.")

litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py

@@ -337,7 +337,7 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_trion_t120_bga576_dev_kit.Platform, description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit")
     parser.add_target_argument("--flash",          action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",   default=75e6,        help="System clock frequency.")

litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py

@@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit")
     parser.add_target_argument("--flash",          action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",   default=100e6,        help="System clock frequency.")

litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py

@@ -64,7 +64,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_trion_t20_mipi_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 MIPI Dev Kit")
     parser.add_target_argument("--sys-clk-freq",   default=100e6,        help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")

litex_boards/targets/efinix_xyloni_dev_kit.py

@@ -81,7 +81,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=efinix_xyloni_dev_kit.Platform, description="LiteX SoC on Efinix Xyloni Dev Kit")
     parser.add_target_argument("--flash", action="store_true",           help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",      default=33.333e6,  help="System clock frequency.")

litex_boards/targets/ego1.py

@@ -59,7 +59,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=ego1.Platform, description="LiteX SoC on EGO1")
     parser.add_target_argument("--flash",               action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")

litex_boards/targets/enclustra_mercury_kx2.py

@@ -75,7 +75,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=enclustra_mercury_kx2.Platform, description="LiteX SoC on KX2")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/enclustra_mercury_xu5.py

@@ -83,7 +83,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=enclustra_mercury_xu5.Platform, description="LiteX SoC on Mercury XU5")
     parser.add_target_argument("--sys-clk-freq", default=125e6,       help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/fairwaves_xtrx.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=fairwaves_xtrx.Platform, description="LiteX SoC on Fairwaves XTRX")
     parser.add_target_argument("--flash",           action="store_true", help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",    default=125e6,       help="System clock frequency.")

litex_boards/targets/fpc_iii.py

@@ -123,7 +123,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=fpc_iii.Platform, description="LiteX SoC on FPC-III")
     parser.add_target_argument("--sys-clk-freq",    default=80e6,        help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/fpgawars_alhambra2.py

@@ -74,7 +74,7 @@ class BaseSoC(SoCCore):
 
 def main():
 
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
 
     parser = LiteXArgumentParser(platform=fpgawars_alhambra2.Platform, description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
     parser.add_target_argument("--sys-clk-freq",      default=12e6,        help="System clock frequency.")

litex_boards/targets/gsd_butterstick.py

@@ -151,7 +151,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=gsd_butterstick.Platform, description="LiteX SoC on ButterStick")
     parser.add_target_argument("--programmer",      default="jtag",         help="Programming interface (jtag or dfu).")
     parser.add_target_argument("--sys-clk-freq",    default=75e6,           help="System clock frequency.")

litex_boards/targets/gsd_orangecrab.py

@@ -195,7 +195,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=gsd_orangecrab.Platform, description="LiteX SoC on OrangeCrab")
     parser.add_target_argument("--sys-clk-freq",    default=48e6,         help="System clock frequency.")
     parser.add_target_argument("--revision",        default="0.2",        help="Board Revision (0.1 or 0.2).")

litex_boards/targets/hackaday_hadbadge.py

@@ -74,7 +74,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=hackaday_hadbadge.Platform, description="LiteX SoC on Hackaday Badge")
     parser.add_target_argument("--sys-clk-freq", default=48e6,        help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/hpcstore_xc7k420t.py

@@ -138,7 +138,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=hpcstore_xc7k420t.Platform, description="LiteX SoC on AliExpress HPC Store XC7K420T")
     parser.add_target_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--io-voltage",      default="3.3V",       help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'")

litex_boards/targets/icebreaker.py

@@ -132,7 +132,7 @@ def flash(build_dir, build_name, bios_flash_offset):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=icebreaker.Platform, description="LiteX SoC on iCEBreaker")
     parser.add_target_argument("--flash",               action="store_true", help="Flash Bitstream and BIOS.")
     parser.add_target_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency.")

litex_boards/targets/icebreaker_bitsy.py

@@ -144,7 +144,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=icebreaker_bitsy.Platform, description="LiteX SoC on iCEBreaker")
     parser.add_target_argument("--flash",               action="store_true", help="Flash bitstream and BIOS.")
     parser.add_target_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency.")

litex_boards/targets/jungle_electronics_fireant.py

@@ -97,7 +97,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=jungle_electronics_fireant.Platform, description="LiteX SoC on Jungle Electronics FireAnt")
     parser.add_target_argument("--flash", action="store_true",           help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",      default=33.333e6,  help="System clock frequency.")

litex_boards/targets/kosagi_fomu.py

@@ -157,7 +157,7 @@ def flash(build_dir, build_name, bios_flash_offset):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=kosagi_fomu_pvt.Platform, description="LiteX SoC on Fomu")
     parser.add_target_argument("--sys-clk-freq",      default=12e6,        help="System clock frequency.")
     parser.add_target_argument("--bios-flash-offset", default="0x20000",   help="BIOS offset in SPI Flash.")

litex_boards/targets/kosagi_netv2.py

@@ -106,7 +106,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=kosagi_netv2.Platform, description="LiteX SoC on NeTV2")
     parser.add_target_argument("--variant",         default="a7-35",     help="Board variant (a7-35 or a7-100).")
     parser.add_target_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency.")

litex_boards/targets/krtkl_snickerdoodle.py

@@ -105,7 +105,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=krtkl_snickerdoodle.Platform, description="LiteX SoC on Snickerdoodle")
     parser.add_target_argument("--variant",      default="z7-10",     help="Board variant (z7-10 or z7-20).")
     parser.add_target_argument("--ext-clk-freq", default=10e6,  type=float, help="External Clock Frequency.")

litex_boards/targets/lambdaconcept_ecpix5.py

@@ -220,7 +220,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lambdaconcept_ecpix5.Platform, description="LiteX SoC on ECPIX-5")
     parser.add_target_argument("--flash",           action="store_true", help="Flash bitstream to SPI Flash.")
     parser.add_target_argument("--device",          default="85F",       help="ECP5 device (45F or 85F).")

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -91,7 +91,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_crosslink_nx_evn.Platform, description="LiteX SoC on Crosslink-NX Eval Board")
     parser.add_target_argument("--device",        default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
     parser.add_target_argument("--sys-clk-freq",  default=75e6,               help="System clock frequency.")

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -99,7 +99,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_crosslink_nx_vip.Platform, description="LiteX SoC on Crosslink-NX VIP Board")
     parser.add_target_argument("--sys-clk-freq",  default=75e6,        help="System clock frequency.")
     parser.add_target_argument("--with-hyperram", default="none",      help="Enable use of HyperRAM chip (none, 0 or 1).")

litex_boards/targets/lattice_ecp5_evn.py

@@ -63,7 +63,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_ecp5_evn.Platform, description="LiteX SoC on ECP5 Evaluation Board")
     parser.add_target_argument("--sys-clk-freq", default=60e6,        help="System clock frequency.")
     parser.add_target_argument("--x5-clk-freq",  type=int,            help="Use X5 oscillator as system clock at the specified frequency.")

litex_boards/targets/lattice_ecp5_vip.py

@@ -186,7 +186,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_ecp5_vip.Platform, description="LiteX SoC on ECP5 Evaluation Board")
     parser.add_target_argument("--sys-clk-freq", default=60e6,        help="System clock frequency (default: 60MHz)")
     args = parser.parse_args()

litex_boards/targets/lattice_ice40up5k_evn.py

@@ -129,7 +129,7 @@ def flash(bios_flash_offset, target="lattice_ice40up5k_evn"):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_ice40up5k_evn.Platform, description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
     parser.add_target_argument("--sys-clk-freq",      default=12e6,        help="System clock frequency.")
     parser.add_target_argument("--bios-flash-offset", default="0x20000",   help="BIOS offset in SPI Flash.")

litex_boards/targets/lattice_versa_ecp5.py

@@ -119,7 +119,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=lattice_versa_ecp5.Platform, description="LiteX SoC on Versa ECP5")
     parser.add_target_argument("--sys-clk-freq",    default=75e6,                     help="System clock frequency.")
     parser.add_target_argument("--device",          default="LFE5UM5G",               help="FPGA device (LFE5UM5G or LFE5UM).")

litex_boards/targets/limesdr_mini_v2.py

@@ -136,7 +136,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=limesdr_mini_v2.Platform, description="LiteX SoC on LimeSDR-Mini-V2")
     parser.add_target_argument("--sys-clk-freq", default=80e6,        help="System clock frequency.")
     args = parser.parse_args()

litex_boards/targets/linsn_rv901t.py

@@ -89,7 +89,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=linsn_rv901t.Platform, description="LiteX SoC on Linsn RV901T")
     parser.add_target_argument("--sys-clk-freq",  default=75e6,        help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/litex_acorn_baseboard.py

@@ -119,7 +119,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=litex_acorn_baseboard.Platform, description="LiteX SoC on LiteX Acorn Baseboard")
     parser.add_target_argument("--flash",        action="store_true", help="Flash bitstream to SPI Flash.")
     parser.add_target_argument("--sys-clk-freq", default=75e6,        help="System clock frequency.")

litex_boards/targets/logicbone.py

@@ -142,7 +142,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=logicbone.Platform, description="LiteX SoC on Logicbone")
     parser.add_target_argument("--sys-clk-freq",   default=75e6,          help="System clock frequency.")
     parser.add_target_argument("--device",         default="45F",         help="FPGA device (45F or 85F).")

litex_boards/targets/machdyne_schoko.py

@@ -171,7 +171,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=machdyne_schoko.Platform, description="LiteX SoC on Schoko")
     parser.add_target_argument("--flash",           action="store_true",  help="Flash bitstream to MMOD.")
     parser.add_target_argument("--sys-clk-freq",    default=40e6,         help="System clock frequency.")

litex_boards/targets/micronova_mercury2.py

@@ -131,7 +131,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=micronova_mercury2.Platform, description="LiteX SoC on MicroNova Mercury2")
     parser.add_target_argument("--variant",      default="a7-35",     help="Board variant (a7-35 or a7-100).")
     parser.add_target_argument("--sys-clk-freq", default=50e6,        help="System clock frequency.")

litex_boards/targets/mist.py

@@ -85,7 +85,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=mist.Platform, description="LiteX SoC on MIST")
     parser.add_target_argument("--sys-clk-freq",        default=50e6,        help="System clock frequency.")
     parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")

litex_boards/targets/mnt_rkx7.py

@@ -193,7 +193,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=mnt_rkx7.Platform, description="LiteX SoC on MNT-RKX7")
     parser.add_target_argument("--sys-clk-freq",    default=100e6,                      help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash",  action="store_true", default=True,  help="Enable SPI Flash (MMAPed).")

litex_boards/targets/muselab_icesugar.py

@@ -107,7 +107,7 @@ def flash(bios_flash_offset):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=muselab_icesugar.Platform, description="LiteX SoC on iCEBreaker")
     parser.add_target_argument("--flash",               action="store_true", help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency.")

litex_boards/targets/muselab_icesugar_pro.py

@@ -142,7 +142,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=muselab_icesugar_pro.Platform, description="LiteX SoC on Colorlight i5")
     parser.add_target_argument("--sys-clk-freq",     default=50e6,             help="System clock frequency.")
     sdopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/myminieye_runber.py

@@ -56,7 +56,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=myminieye_runber.Platform, description="LiteX SoC on Runber")
     parser.add_target_argument("--flash",       action="store_true", help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",default=12e6,        help="System clock frequency.")

litex_boards/targets/newae_cw305.py

@@ -81,7 +81,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=newae_cw305.Platform, description="LiteX SoC on NewAE-CW305")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
 

litex_boards/targets/numato_aller.py

@@ -96,7 +96,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=numato_aller.Platform, description="LiteX SoC on Aller")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")

litex_boards/targets/numato_mimas_a7.py

@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=numato_mimas_a7.Platform, description="LiteX SoC on Mimas A7")
     parser.add_target_argument("--sys-clk-freq",  default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")

litex_boards/targets/numato_nereid.py

@@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=numato_nereid.Platform, description="LiteX SoC on Nereid")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")

litex_boards/targets/numato_tagus.py

@@ -96,7 +96,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=numato_tagus.Platform, description="LiteX SoC on Tagus")
     parser.add_target_argument("--sys-clk-freq", default=100e6,       help="System clock frequency.")
     parser.add_target_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")

litex_boards/targets/pano_logic_g2.py

@@ -79,7 +79,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=pano_logic_g2.Platform, description="LiteX SoC on Pano Logic G2")
     parser.add_target_argument("--revision",        default="c",                      help="Board revision (b or c).")
     parser.add_target_argument("--sys-clk-freq",    default=50e6,                     help="System clock frequency.")

litex_boards/targets/qmtech_10cl006.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_10cl006.Platform, description="LiteX SoC on QMTECH 10CL006")
     parser.add_target_argument("--sys-clk-freq",        default=50e6,        help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",          default="1:2",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/qmtech_5cefa2.py

@@ -131,7 +131,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_5cefa2.Platform, description="LiteX SoC on QMTECH 5CEFA2")
     parser.add_target_argument("--sys-clk-freq", default=105e6,       help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",   default="1:1",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/qmtech_ep4ce15_starter_kit.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_ep4ce15_starter_kit.Platform, description="LiteX SoC on QMTECH EP4CE15")
     parser.add_target_argument("--sys-clk-freq",  default=50e6,        help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",    default="1:1",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/qmtech_ep4cex5.py

@@ -129,7 +129,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_ep4cex5.Platform, description="LiteX SoC on QMTECH EP4CE15")
     parser.add_target_argument("--variant",      default="ep4ce15",   help="Board variant (ep4ce15 or ep4ce55).")
     parser.add_target_argument("--sys-clk-freq", default=50e6,        help="System clock frequency.")

litex_boards/targets/qmtech_ep4cgx150.py

@@ -128,7 +128,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_ep4cgx150.Platform, description="LiteX SoC on QMTECH EP4CE15")
     parser.add_target_argument("--sys-clk-freq", default=80e6,        help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",   default="1:1",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/qmtech_wukong.py

@@ -127,7 +127,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board")
     parser.add_target_argument("--sys-clk-freq",    default=100e6,                    help="System clock frequency.")
     parser.add_target_argument("--board-version",   default=1,                        help="Board version (1 or 2).")

litex_boards/targets/qmtech_xc7a35t.py

@@ -140,7 +140,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_xc7a35t.Platform, description="LiteX SoC on QMTech XC7A35T")
     parser.add_target_argument("--sys-clk-freq",        default=100e6,                    help="System clock frequency.")
     parser.add_target_argument("--with-daughterboard",  action="store_true",              help="Board plugged into the QMTech daughterboard.")

litex_boards/targets/quicklogic_quickfeather.py

@@ -89,7 +89,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=quicklogic_quickfeather.Platform, description="LiteX SoC on QuickLogic QuickFeather")
     parser.set_defaults(cpu_type="eos_s3")
     args = parser.parse_args()

litex_boards/targets/qwertyembedded_beaglewire.py

@@ -108,7 +108,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qwertyembedded_beaglewire.Platform, description="LiteX SoC on Beaglewire")
     parser.add_target_argument("--bios-flash-offset", default="0x60000",   help="BIOS offset in SPI Flash.")
     parser.add_target_argument("--sys-clk-freq",      default=50e6,        help="System clock frequency.")

litex_boards/targets/radiona_ulx3s.py

@@ -142,7 +142,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=radiona_ulx3s.Platform, description="LiteX SoC on ULX3S")
     parser.add_target_argument("--device",          default="LFE5U-45F",   help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
     parser.add_target_argument("--revision",        default="2.0",         help="Board revision (2.0 or 1.7).")

litex_boards/targets/rcs_arctic_tern_bmc_card.py

@@ -154,7 +154,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=rcs_arctic_tern_bmc_card.Platform, description="LiteX SoC on Arctic Tern (BMC card carrier)")
     parser.add_target_argument("--sys-clk-freq", default=60e6,        help="System clock frequency (default: 60MHz)")
     ethopts = parser.target_group.add_mutually_exclusive_group()

litex_boards/targets/redpitaya.py

@@ -94,7 +94,7 @@ class BaseSoC(SoCCore):
 
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=redpitaya.Platform, description="LiteX SoC on Zedboard")
     parser.add_target_argument("--sys-clk-freq", default=100e6,         help="System clock frequency.")
     parser.add_target_argument("--board",        default="redpitaya14", help="Board type (redpitaya14 or redpitaya16).")

litex_boards/targets/rz_easyfpga.py

@@ -90,7 +90,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=rz_easyfpga.Platform, description="LiteX SoC on RZ-EasyFPGA")
     parser.add_target_argument("--sys-clk-freq", default=50e6,        help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",   default="1:1",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/saanlima_pipistrello.py

@@ -189,7 +189,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=saanlima_pipistrello.Platform, description="LiteX SoC on Pipistrello")
     args = parser.parse_args()
 

litex_boards/targets/scarabhardware_minispartan6.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=scarabhardware_minispartan6.Platform, description="LiteX SoC on MiniSpartan6")
     parser.add_target_argument("--sys-clk-freq",           default=80e6,        help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",             default="1:1",       help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")

litex_boards/targets/seeedstudio_spartan_edge_accelerator.py

@@ -105,7 +105,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=seeedstudio_spartan_edge_accelerator.Platform, description="LiteX SoC on Spartan Edge Accelerator")
     parser.add_target_argument("--sys-clk-freq",        default=100e6,        help="System clock frequency.")
     parser.add_target_argument("--with-jtagbone",       action="store_true",  help="Enable Jtagbone support.")

litex_boards/targets/siglent_sds1104xe.py

@@ -161,7 +161,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=siglent_sds1104xe.Platform, description="LiteX SoC on SDS1104X-E")
     parser.add_target_argument("--sys-clk-freq",   default=100e6,                    help="System clock frequency.")
     parser.add_target_argument("--with-etherbone", action="store_true",              help="Enable Etherbone support.")

litex_boards/targets/simple.py

@@ -44,7 +44,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(description="Generic LiteX SoC")
     parser.add_target_argument("platform", help="Module name of the platform to build for.")
     args = parser.parse_args()

litex_boards/targets/sipeed_tang_nano.py

@@ -84,7 +84,7 @@ class BaseSoC(SoCMini):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sipeed_tang_nano.Platform, description="LiteX SoC on Tang Nano")
     parser.add_target_argument("--flash",       action="store_true", help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",default=48e6,        help="System clock frequency.")

litex_boards/targets/sipeed_tang_nano_4k.py

@@ -137,7 +137,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sipeed_tang_nano_4k.Platform, description="LiteX SoC on Tang Nano 4K")
     parser.add_target_argument("--flash",       action="store_true", help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",default=27e6,        help="System clock frequency.")

litex_boards/targets/sipeed_tang_nano_9k.py

@@ -131,7 +131,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sipeed_tang_nano_9k.Platform, description="LiteX SoC on Tang Nano 9K")
     parser.add_target_argument("--flash",                action="store_true",      help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",         default=27e6,             help="System clock frequency.")

litex_boards/targets/sipeed_tang_primer.py

@@ -59,7 +59,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sipeed_tang_primer.Platform, description="LiteX SoC on Tang Primer")
     parser.add_target_argument("--flash",       action="store_true", help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",default=24e6,        help="System clock frequency.")

litex_boards/targets/sipeed_tang_primer_20k.py

@@ -210,7 +210,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sipeed_tang_primer_20k.Platform, description="LiteX SoC on Tang Primer 20K")
     parser.add_target_argument("--dock",         default="standard",    help="Dock version (standard (default) or lite.")
     parser.add_target_argument("--flash",        action="store_true",   help="Flash Bitstream.")

litex_boards/targets/sitlinv_a_e115fb.py

@@ -57,7 +57,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    from litex.build.argument_parser import LiteXArgumentParser
+    from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=sitlinv_a_e115fb.Platform, description="LiteX SoC on A-E115FB")
     parser.add_target_argument("--sys-clk-freq", default=50e6,        help="System clock frequency.")
     args = parser.parse_args()