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Merge pull request #131 from antmicro/sync_arty 

Sync Arty Board files with main LiteX repository
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enjoy-digital 2020-12-07 21:43:34 +01:00 committed by GitHub
parent 0b8a01f929 18337cdf25
commit 3463e3be49
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2 changed files with 20 additions and 13 deletions
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5
litex_boards/platforms/arty.py
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@ -312,12 +312,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100" default_clk_name = "clk100"
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self, variant="a7-35"): def __init__(self, variant="a7-35", toolchain="vivado"):
device = { device = {
"a7-35": "xc7a35ticsg324-1L", "a7-35": "xc7a35ticsg324-1L",
"a7-100": "xc7a100tcsg324-1" "a7-100": "xc7a100tcsg324-1"
}[variant] }[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \ self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \ self.toolchain.additional_commands = \
@ -331,4 +331,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
from litex.build.xilinx import symbiflow
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)

28
litex_boards/targets/arty.py
View File

@ -4,6 +4,7 @@
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -54,13 +55,13 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs): def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
platform = arty.Platform() platform = arty.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7", ident = "LiteX SoC on Arty A7",
ident_version = True, ident_version = ident_version,
**kwargs) **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
@ -104,13 +105,15 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
vivado_build_args(parser) vivado_build_args(parser)
@ -118,9 +121,11 @@ def main():
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC( soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
ident_version = args.no_ident_version,
**soc_sdram_argdict(args) **soc_sdram_argdict(args)
) )
assert not (args.with_spi_sdcard and args.with_sdcard) assert not (args.with_spi_sdcard and args.with_sdcard)
@ -130,7 +135,8 @@ def main():
if args.with_sdcard: if args.with_sdcard:
soc.add_sdcard() soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build) builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load: if args.load:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()