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Merge pull request #467 from mlaga97/master 

Allow building digilent_arty using f4pga
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enjoy-digital 2023-01-07 09:49:31 +01:00 committed by GitHub
parent 6658f20682 7a911b8ff6
commit 3ca0c7a035
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1 changed files with 5 additions and 3 deletions
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litex_boards/targets/digilent_arty.py
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@ -91,11 +91,13 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs)
# XADC ------------------------------------------------------------------------------------- # XADC -------------------------------------------------------------------------------------
self.xadc = XADC() if toolchain == "vivado":
self.xadc = XADC()
# DNA -------------------------------------------------------------------------------------- # DNA --------------------------------------------------------------------------------------
self.dna = DNA() if toolchain == "vivado":
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size: