Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

use bistream compression on those large devices

This commit is contained in:
Hans Baier 2023-03-21 09:25:56 +07:00
parent 0125ae4271
commit 40c8e62b09
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex_boards/platforms/qmtech_artix7_fbg484.py
View File

@ -162,7 +162,8 @@ class Platform(Xilinx7SeriesPlatform):
Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
@ -178,4 +179,4 @@ class Platform(Xilinx7SeriesPlatform):
def do_finalize(self, fragment):
Xilinx7SeriesPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

3
litex_boards/platforms/qmtech_artix7_fgg676.py
View File

@ -162,7 +162,8 @@ class Platform(Xilinx7SeriesPlatform):
Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]