mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
pcbarts_klusterlab: add video and ethernet, fix gtp definitions
This commit is contained in:
Hans Baier
parent
22bdb575d1
commit
4756b22649
2 changed files with 91 additions and 40 deletions
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@ -211,17 +211,15 @@ _io = [
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# Subsignal("scl", Pins(""), IOStandard("LVCMOS33")),
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# Subsignal("sda", Pins(""), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("N26"), IOStandard("LVCMOS33")),
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Subsignal("hdp", Pins("M26"), IOStandard("LVCMOS25")),
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Subsignal("hdp", Pins("M26"), IOStandard("LVCMOS33")),
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),
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# SFP0
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("sfp_tx", 0,
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Subsignal("p", Pins("P2")),
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Subsignal("n", Pins("P1"))
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("R4")),
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Subsignal("n", Pins("R3"))
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("sfp", 0,
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Subsignal("txp", Pins("P2")),
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Subsignal("txn", Pins("P1")),
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Subsignal("rxp", Pins("R4")),
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Subsignal("rxn", Pins("R3"))
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),
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("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 0, Pins("T19"), IOStandard("LVCMOS33")),
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@ -229,13 +227,11 @@ _io = [
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("sfp_act", 0, Pins("T25"), IOStandard("LVCMOS33")),
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# SFP1
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("sfp_tx", 1,
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Subsignal("p", Pins("M2")),
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Subsignal("n", Pins("M1")),
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),
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("sfp_rx", 1,
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Subsignal("p", Pins("N4")),
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Subsignal("n", Pins("N3")),
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("sfp", 1,
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Subsignal("txp", Pins("M2")),
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Subsignal("txn", Pins("M1")),
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Subsignal("rxp", Pins("N4")),
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Subsignal("rxn", Pins("N3")),
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),
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("sfp_tx_disable_n", 1, Pins("N18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 1, Pins("M19"), IOStandard("LVCMOS33")),
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@ -243,13 +239,11 @@ _io = [
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("sfp_act", 1, Pins("R23"), IOStandard("LVCMOS33")),
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# SFP2
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("sfp_tx", 2,
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Subsignal("p", Pins("K2")),
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Subsignal("n", Pins("K1")),
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),
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("sfp_rx", 2,
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Subsignal("p", Pins("L4")),
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Subsignal("n", Pins("L3")),
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("sfp", 2,
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Subsignal("txp", Pins("K2")),
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Subsignal("txn", Pins("K1")),
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Subsignal("rxp", Pins("L4")),
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Subsignal("rxn", Pins("L3")),
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),
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("sfp_tx_disable_n", 2, Pins("N17"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 2, Pins("R17"), IOStandard("LVCMOS33")),
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@ -257,13 +251,11 @@ _io = [
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("sfp_act", 2, Pins("N21"), IOStandard("LVCMOS33")),
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# SFP3
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("sfp_tx", 3,
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Subsignal("p", Pins("H2")),
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Subsignal("n", Pins("H1")),
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),
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("sfp_rx", 3,
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Subsignal("p", Pins("J4")),
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Subsignal("n", Pins("J3")),
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("sfp", 3,
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Subsignal("txp", Pins("H2")),
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Subsignal("txn", Pins("H1")),
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Subsignal("rxp", Pins("J4")),
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Subsignal("rxn", Pins("J3")),
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),
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("sfp_tx_disable_n", 3, Pins("P16"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 3, Pins("R16"), IOStandard("LVCMOS33")),
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@ -14,10 +14,13 @@ from litex.gen import *
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from litex_boards.platforms import pcbarts_klusterlab
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoS7HDMIPHY
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from liteeth.phy.k7_1000basex import K7_1000BASEX
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from litedram.modules import MT41J256M16
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from litedram.common import PHYPadsReducer
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@ -26,16 +29,18 @@ from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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cpu_reset = Signal()
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self.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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@ -44,18 +49,36 @@ class _CRG(LiteXModule):
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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self.comb += [
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cpu_reset.eq(platform.request("cpu_reset")),
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pll.reset.eq(cpu_reset | self.rst),
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]
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# Video PLL.
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if with_video_pll:
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self.video_pll = video_pll = S7MMCM(speedgrade=-1)
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video_pll.reset.eq(cpu_reset | self.rst)
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video_pll.register_clkin(ClockSignal(), sys_clk_freq)
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video_pll.create_clkout(self.cd_hdmi, 40e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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with_ethernet = False,
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with_etherbone = False,
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with_led_chaser = True,
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with_ethernet = False,
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_video_colorbars = False,
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**kwargs):
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platform = pcbarts_klusterlab.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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with_video_pll = (with_video_terminal or with_video_framebuffer or with_video_colorbars)
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self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_pll)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on PCBArts KlusterLab", **kwargs)
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@ -73,6 +96,33 @@ class BaseSoC(SoCCore):
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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# phy
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refclk = Signal()
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self.comb += [
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refclk.eq(ClockSignal("idelay")),
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self.platform.request("sfp_tx_disable_n", 0).eq(1)
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]
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self.ethphy = K7_1000BASEX(
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refclk_or_clk_pads = refclk,
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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self.add_ethernet(phy=self.ethphy)
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self.add_etherbone(phy=self.ethphy, ip_address="192.168.0.222")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
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# Video ------------------------------------------------------------------------------------
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if (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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@ -85,13 +135,22 @@ def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=pcbarts_klusterlab.Platform, description="LiteX SoC on PCBArts KlusterLab")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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sys_clk_freq = args.sys_clk_freq,
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with_ethernet = args.with_ethernet,
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with_video_colorbars = args.with_video_colorbars,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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