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targets/spiflash: Simplify self.cpu.set_reset_address call.

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This commit is contained in:
Florent Kermarrec 2022-01-07 15:19:23 +01:00
parent 30cacc19c2
commit 4b6a9b2cf0
10 changed files with 10 additions and 30 deletions
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2
litex_boards/targets/1bitsquared_icebreaker.py
View file

@ -112,8 +112,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Video ------------------------------------------------------------------------------------

2
litex_boards/targets/1bitsquared_icebreaker_bitsy.py
View file

@ -107,8 +107,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/efinix_xyloni_dev_kit.py
View file

@ -74,8 +74,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/kosagi_fomu.py
View file

@ -125,8 +125,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/lattice_ice40up5k_evn.py
View file

@ -93,8 +93,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/muselab_icesugar.py
View file

@ -93,8 +93,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/qwertyembedded_beaglewire.py
View file

@ -100,8 +100,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/sipeed_tang_nano_4k.py
View file

@ -101,8 +101,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# HyperRAM ---------------------------------------------------------------------------------

2
litex_boards/targets/tinyfpga_bx.py
View file

@ -53,8 +53,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/trenz_tec0117.py
View file

@ -87,8 +87,6 @@ class BaseSoC(SoCCore):
size = 32*kB,
linker = True)
)
# Set CPU reset address to ROM.
if hasattr(self.cpu, "set_reset_address"):
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# SDR SDRAM --------------------------------------------------------------------------------