Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #174 from yetifrisstlama/vc707_clk 

vc707.py: clk156 add missing constraint
This commit is contained in:
enjoy-digital 2021-02-09 10:44:49 +01:00 committed by GitHub
parent fef9dd036a 7442c2dada
commit 52d5787ade
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
litex_boards/platforms/vc707.py
View File

@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6)
self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)