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Merge pull request #174 from yetifrisstlama/vc707_clk 

vc707.py: clk156 add missing constraint
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enjoy-digital 2021-02-09 10:44:49 +01:00 committed by GitHub
parent fef9dd036a 7442c2dada
commit 52d5787ade
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litex_boards/platforms/vc707.py
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@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6)
self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)