targets: Remove SpiFlash imports (Obsolete since integration is provided by LiteX).

litex_boards/targets/1bitsquared_icebreaker.py

@@ -26,7 +26,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import icebreaker
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/1bitsquared_icebreaker_bitsy.py

@@ -25,7 +25,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import icebreaker_bitsy
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/colorlight_i5.py

@@ -19,7 +19,6 @@ from litex_boards.platforms import colorlight_i5
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.cores.clock import *
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.video import VideoECP5HDMIPHY

litex_boards/targets/digilent_cmod_a7.py

@@ -17,7 +17,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex_boards.platforms import digilent_cmod_a7
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/digilent_nexys4.py

@@ -17,7 +17,6 @@ from litex.build.io import CRG
 
 from litex_boards.platforms import digilent_nexys4
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/kosagi_fomu.py

@@ -18,7 +18,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import fomu_pvt
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -17,7 +17,6 @@ from litex_boards.platforms import crosslink_nx_evn
 
 from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.clock import NXPLL
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *
 

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -22,7 +22,6 @@ from litex_boards.platforms import crosslink_nx_vip
 from litehyperbus.core.hyperbus import HyperRAM
 
 from litex.soc.cores.ram import NXLRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *
 

litex_boards/targets/lattice_ice40up5k_evn.py

@@ -21,7 +21,6 @@ from litex_boards.platforms import lattice_ice40up5k_evn
 from litex.build.lattice.programmer import IceStormProgrammer
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/micronova_mercury2.py

@@ -17,7 +17,6 @@ from litex.build.io import CRG
 from litex_boards.platforms import micronova_mercury2
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion

litex_boards/targets/muselab_icesugar_pro.py

@@ -19,7 +19,6 @@ from litex_boards.platforms import muselab_icesugar_pro
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.cores.clock import *
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.video import VideoECP5HDMIPHY

litex_boards/targets/tinyfpga_bx.py

@@ -16,7 +16,6 @@ from litex.build.io import CRG
 
 from litex_boards.platforms import tinyfpga_bx
 
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *