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colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)

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Florent Kermarrec 2020-01-23 13:16:36 +01:00
parent 4fb89fc9c5
commit 55c0b781e4
1 changed files with 2 additions and 2 deletions
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litex_boards/partner/targets/colorlight_5a_75b.py
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@ -68,8 +68,8 @@ class EtherboneSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9, # No FPGA delay (Clk/Data delay added by PCB/PHY)
rx_delay = 0e-9) # No FPGA delay (Clk/Data delay added by PCB/PHY)
tx_delay = 0e-9, # 0ns FPGA delay (Clk delay added by PHY)
rx_delay = 2e-9) # 2ns FPGA delay to compensate Clk routing to IDDRX1F
self.add_csr("ethphy")
# core
self.submodules.ethcore = LiteEthUDPIPCore(