colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
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@ -68,8 +68,8 @@ class EtherboneSoC(BaseSoC):
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self.submodules.ethphy = LiteEthPHYRGMII(
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy),
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pads = self.platform.request("eth", eth_phy),
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tx_delay = 0e-9, # No FPGA delay (Clk/Data delay added by PCB/PHY)
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tx_delay = 0e-9, # 0ns FPGA delay (Clk delay added by PHY)
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rx_delay = 0e-9) # No FPGA delay (Clk/Data delay added by PCB/PHY)
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rx_delay = 2e-9) # 2ns FPGA delay to compensate Clk routing to IDDRX1F
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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# core
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# core
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self.submodules.ethcore = LiteEthUDPIPCore(
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self.submodules.ethcore = LiteEthUDPIPCore(
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