gsd_butterstick: Add initial DDR3 support.
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
This commit is contained in:
Florent Kermarrec
parent
1f25a98476
commit
55ea71bd01
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@ -29,6 +29,32 @@ _io_r1_0 = [
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("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")),
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("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"G16 E19 E20 F16 F19 E16 F17 L20 "
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"M20 E18 G18 D18 H18 C18 D17 G20 "),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("H16 F20 H20"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("K18"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("J17"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("G19"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("J20 J16"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("U20 L18"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"U19 T18 U18 R20 P18 P19 P20 N20",
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"L19 L17 L16 R16 N18 R17 N17 P17"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("T19 N16"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("C20 J19"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("F18 J18"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("K20 H17"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("E17"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST")
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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@ -17,6 +17,8 @@ import sys
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import butterstick
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -26,6 +28,9 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K256M16
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ---------------------------------------------------------------------------------------------
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@ -33,11 +38,17 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk30 = platform.request("clk30")
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rst_n = platform.request("user_btn", 0)
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@ -50,10 +61,31 @@ class _CRG(Module):
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk30, 30e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout,
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),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -73,6 +105,19 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K256M16(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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@ -98,7 +143,7 @@ def main():
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)")
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parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)")
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ethopts = parser.add_mutually_exclusive_group()
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