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litex-boards
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targets: Use "" for strings.

This commit is contained in:
Florent Kermarrec 2022-04-21 15:48:29 +02:00
parent 353aba0359
commit 575d681891
8 changed files with 26 additions and 26 deletions
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10
litex_boards/targets/alinx_axu2cga.py
View File

@ -74,10 +74,10 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False
self.mem_map = {
'csr': 0x8000_0000, # Zynq GP0 default
"csr": 0x8000_0000, # Zynq GP0 default
}
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs)
@ -90,7 +90,7 @@ class BaseSoC(SoCCore):
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(2, 32),
wishbone = wb_lpd,
base_address = self.mem_map['csr'])
base_address = self.mem_map["csr"])
self.bus.add_master(master=wb_lpd)
self.bus.add_region("sram", SoCRegion(
@ -102,7 +102,7 @@ class BaseSoC(SoCCore):
size = 512 * 1024 * 1024 // 8,
linker = True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127
self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:

2
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
View File

@ -167,7 +167,7 @@ class BaseSoC(SoCCore):
class LiteDRAMSettingsEncoder(json.JSONEncoder):
def default(self, o):
if isinstance(o, (ControllerSettings, GeomSettings, PhySettings, TimingSettings)):
ignored = ['self', 'refresh_cls']
ignored = ["self", "refresh_cls"]
return {k: v for k, v in vars(o).items() if k not in ignored}
elif isinstance(o, Signal) and isinstance(o.reset, Constant):
return o.reset

6
litex_boards/targets/digilent_arty_z7.py
View File

@ -61,8 +61,8 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False
self.mem_map = {
'csr': 0x4000_0000, # Zynq GP0 default
}
@ -82,7 +82,7 @@ class BaseSoC(SoCCore):
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = self.mem_map['csr'])
base_address = self.mem_map["csr"])
self.bus.add_master(master=wb_gp0)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/digilent_zedboard.py
View File

@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
size = 256 * 1024 * 1024 // 8,
linker = True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687
self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:

2
litex_boards/targets/krtkl_snickerdoodle.py
View File

@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = self.mem_map['csr'])
base_address = self.mem_map["csr"])
self.bus.add_master(master=wb_gp0)
# Leds -------------------------------------------------------------------------------------

2
litex_boards/targets/quicklogic_quickfeather.py
View File

@ -54,7 +54,7 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
kwargs["with_uart"] = False
if kwargs.get("cpu_type", None) == "eos_s3":
kwargs['integrated_sram_size'] = 0
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QuickLogic QuickFeather", **kwargs)
# EOS-S3 Integration -----------------------------------------------------------------------

4
litex_boards/targets/xilinx_kv260.py
View File

@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KV260", **kwargs)
# ZynqMP Integration -----------------------------------------------------------------------
@ -142,7 +142,7 @@ class BaseSoC(SoCCore):
size = 512 * 1024 * 1024 // 8,
linker = True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1333333008
self.constants["CONFIG_CLOCK_FREQUENCY"] = 1333333008
def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)

4
litex_boards/targets/xilinx_zcu216.py
View File

@ -55,7 +55,7 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU216", **kwargs)
# ZynqMP Integration -----------------------------------------------------------------------
@ -122,7 +122,7 @@ class BaseSoC(SoCCore):
size = 512 * 1024 * 1024 // 8,
linker = True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1200000000
self.constants["CONFIG_CLOCK_FREQUENCY"] = 1200000000
# LEDs -------------------------------------------------------------------------------------
if with_led_chaser: