targets: Use "" for strings.
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@ -74,10 +74,10 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynqmp":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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kwargs["integrated_sram_size"] = 0
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kwargs["with_uart"] = False
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self.mem_map = {
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'csr': 0x8000_0000, # Zynq GP0 default
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"csr": 0x8000_0000, # Zynq GP0 default
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}
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs)
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@ -90,7 +90,7 @@ class BaseSoC(SoCCore):
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(2, 32),
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wishbone = wb_lpd,
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base_address = self.mem_map['csr'])
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base_address = self.mem_map["csr"])
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self.bus.add_master(master=wb_lpd)
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self.bus.add_region("sram", SoCRegion(
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@ -102,7 +102,7 @@ class BaseSoC(SoCCore):
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size = 512 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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@ -167,7 +167,7 @@ class BaseSoC(SoCCore):
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class LiteDRAMSettingsEncoder(json.JSONEncoder):
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def default(self, o):
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if isinstance(o, (ControllerSettings, GeomSettings, PhySettings, TimingSettings)):
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ignored = ['self', 'refresh_cls']
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ignored = ["self", "refresh_cls"]
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return {k: v for k, v in vars(o).items() if k not in ignored}
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elif isinstance(o, Signal) and isinstance(o.reset, Constant):
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return o.reset
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@ -61,8 +61,8 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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kwargs["integrated_sram_size"] = 0
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kwargs["with_uart"] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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@ -82,7 +82,7 @@ class BaseSoC(SoCCore):
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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base_address = self.mem_map["csr"])
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self.bus.add_master(master=wb_gp0)
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# Leds -------------------------------------------------------------------------------------
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@ -78,15 +78,15 @@ class BaseSoC(SoCCore):
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self.bus.add_master(master=wb_gp0)
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self.bus.add_region("sram", SoCRegion(
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origin=self.cpu.mem_map["sram"],
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size=512 * 1024 * 1024 - self.cpu.mem_map["sram"])
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origin = self.cpu.mem_map["sram"],
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size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"])
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.cpu.mem_map["rom"],
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size=256 * 1024 * 1024 // 8,
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linker=True)
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origin = self.cpu.mem_map["rom"],
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size = 256 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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base_address = self.mem_map["csr"])
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self.bus.add_master(master=wb_gp0)
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# Leds -------------------------------------------------------------------------------------
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@ -54,7 +54,7 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["with_uart"] = False
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if kwargs.get("cpu_type", None) == "eos_s3":
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kwargs['integrated_sram_size'] = 0
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QuickLogic QuickFeather", **kwargs)
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# EOS-S3 Integration -----------------------------------------------------------------------
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@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynqmp":
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kwargs['integrated_sram_size'] = 0
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KV260", **kwargs)
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# ZynqMP Integration -----------------------------------------------------------------------
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@ -134,15 +134,15 @@ class BaseSoC(SoCCore):
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base_address = self.mem_map["csr"])
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self.bus.add_master(master=wb_gp0)
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self.bus.add_region("sram", SoCRegion(
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origin=self.cpu.mem_map["sram"],
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size=2 * 1024 * 1024 * 1024) # DDR
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origin = self.cpu.mem_map["sram"],
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size = 2 * 1024 * 1024 * 1024) # DDR
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.cpu.mem_map["rom"],
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size=512 * 1024 * 1024 // 8,
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linker=True)
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origin = self.cpu.mem_map["rom"],
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size = 512 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 1333333008
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 1333333008
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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@ -55,7 +55,7 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynqmp":
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kwargs['integrated_sram_size'] = 0
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU216", **kwargs)
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# ZynqMP Integration -----------------------------------------------------------------------
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@ -122,7 +122,7 @@ class BaseSoC(SoCCore):
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size = 512 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 1200000000
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 1200000000
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# LEDs -------------------------------------------------------------------------------------
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if with_led_chaser:
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