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targets: Switch from bridge to crossover.

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This commit is contained in:
Florent Kermarrec 2022-01-19 17:02:41 +01:00
parent abb54cebb3
commit 5f2ccb2d32
4 changed files with 6 additions and 12 deletions
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2
litex_boards/targets/colorlight_5a_75x.py
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@ -138,7 +138,7 @@ class BaseSoC(SoCCore):
**kwargs) **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n. with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate) self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)

2
litex_boards/targets/decklink_quad_hdmi_recorder.py
View file

@ -11,7 +11,7 @@
# #
# Use: # Use:
# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg # litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
# litex_term bridge # litex_term crossover
import os import os
import argparse import argparse

2
litex_boards/targets/gsd_butterstick.py
View file

@ -10,7 +10,7 @@
# Build/Use: # Build/Use:
# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load # ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
# litex_server --udp # litex_server --udp
# litex_term bridge # litex_term crossover
import os import os
import sys import sys

12
litex_boards/targets/lattice_ice40up5k_evn.py
View file

@ -100,16 +100,10 @@ class BaseSoC(SoCCore):
pads = platform.request_all("user_led_n"), pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
# Add a UART-Wishbone bridge ----------------------------------------- # Add a UARTBone bridge --------------------------------------------------------------------
debug_uart=False debug_uart = False
if debug_uart: if debug_uart:
# This will add a bridge on the second serial port defined in platform self.add_uartbone(name="serial")
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# Flash -------------------------------------------------------------------------------------------- # Flash --------------------------------------------------------------------------------------------