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targets: Switch from bridge to crossover.
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4 changed files with 6 additions and 12 deletions
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@ -138,7 +138,7 @@ class BaseSoC(SoCCore):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
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with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
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@ -11,7 +11,7 @@
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#
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# Use:
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# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
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# litex_term bridge
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# litex_term crossover
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import os
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import argparse
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@ -10,7 +10,7 @@
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# Build/Use:
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# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
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# litex_server --udp
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# litex_term bridge
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# litex_term crossover
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import os
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import sys
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@ -100,16 +100,10 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Add a UART-Wishbone bridge -----------------------------------------
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# Add a UARTBone bridge --------------------------------------------------------------------
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debug_uart = False
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if debug_uart:
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# This will add a bridge on the second serial port defined in platform
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from litex.soc.cores.uart import UARTWishboneBridge
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self.submodules.uart_bridge = UARTWishboneBridge(
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platform.request("serial"),
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sys_clk_freq,
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baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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self.add_uartbone(name="serial")
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# Flash --------------------------------------------------------------------------------------------
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