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Resolve High Density bank IOStandard error 

This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
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Liana Koleva 2023-09-25 12:50:30 +02:00 committed by GitHub
parent 1fb317840f
commit 5f8ac853b1
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1 changed files with 2 additions and 2 deletions
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4
litex_boards/platforms/xilinx_zcu102.py
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@ -13,8 +13,8 @@ from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
_io = [ _io = [
# Clk / Rst # Clk / Rst
("clk125", 0, ("clk125", 0,
Subsignal("p", Pins("G21"), IOStandard("LVDS")), Subsignal("p", Pins("G21"), IOStandard("LVDS_25")),
Subsignal("n", Pins("F21"), IOStandard("LVDS")), Subsignal("n", Pins("F21"), IOStandard("LVDS_25")),
), ),
("clk300", 0, ("clk300", 0,
Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")),