Merge pull request #323 from bl0x/digilent_cmod_a7

Digilent cmod a7: Fix litex build.
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enjoy-digital 2022-01-17 08:20:22 +01:00 committed by GitHub
commit 699c096e91
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2 changed files with 9 additions and 4 deletions

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@ -63,9 +63,13 @@ class Platform(XilinxPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io, _connectors, toolchain="vivado")
def __init__(self, variant="a7-35", toolchain="vivado"):
device = {
"a7-35": "xc7a35tcpg236-1"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
def do_finalize(self,fragment):
XilinxPlatform.do_finalize(self, fragment)
from litex.build.xilinx import symbiflow
self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)

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@ -121,7 +121,7 @@ class BaseSoC(SoCCore):
with_mapped_flash=False,
**kwargs):
platform = digilent_cmod_a7.Platform()
platform = digilent_cmod_a7.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
@ -144,7 +144,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser = argparse.ArgumentParser(description="LiteX SoC on CMOD A7")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
@ -167,6 +167,7 @@ def main():
builder = Builder(soc, **builder_argd)
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if __name__ == "__main__":