Merge pull request #323 from bl0x/digilent_cmod_a7
Digilent cmod a7: Fix litex build.
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commit
699c096e91
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@ -63,9 +63,13 @@ class Platform(XilinxPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io, _connectors, toolchain="vivado")
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35tcpg236-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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def do_finalize(self,fragment):
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XilinxPlatform.do_finalize(self, fragment)
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from litex.build.xilinx import symbiflow
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self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)
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@ -121,7 +121,7 @@ class BaseSoC(SoCCore):
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with_mapped_flash=False,
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**kwargs):
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platform = digilent_cmod_a7.Platform()
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platform = digilent_cmod_a7.Platform(variant=variant, toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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@ -144,7 +144,7 @@ class BaseSoC(SoCCore):
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
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parser = argparse.ArgumentParser(description="LiteX SoC on CMOD A7")
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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@ -167,6 +167,7 @@ def main():
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builder = Builder(soc, **builder_argd)
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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builder.build(**builder_kwargs, run=args.build)
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if __name__ == "__main__":
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