antmicro_sdi_mipi_video_converter: Cleanup/Update to new LiteX conventions.
This commit is contained in:
Florent Kermarrec
parent
fe2be83feb
commit
7b716e4899
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@ -5,30 +5,32 @@
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice import LatticeNexusPlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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from litex.build.lattice.programmer import EcpprogProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk12", 0, Pins("G15"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("J12"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("J11"), IOStandard("LVCMOS33")),
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),
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# Section 7.3 General Purpose LEDs
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# Leds (Section 7.3).
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("user_led", 0, Pins("E15"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("E16"), IOStandard("LVCMOS33")),
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# Section 7.1 DIP Switch
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# DIP Switches (Section 7.1).
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("user_dip_btn", 0, Pins("F15"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("H10"), IOStandard("LVCMOS33")),
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# Section 6.3.1. SPI Configuration
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# SPI Flash (Section 6.3.1.).
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("spiflash", 0,
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Subsignal("cs_n", Pins("C15")),
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Subsignal("clk", Pins("C16")),
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@ -38,17 +40,13 @@ _io = [
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)
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Test and Demo ------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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class Platform(LatticeNexusPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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@ -59,7 +57,7 @@ class Platform(LatticePlatform):
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if device == "LIFCL":
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device == "LIFCL-40-9BG400C"
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assert device in ["LIFCL-40-9BG256C", "LIFCL-40-9BG400C", "LIFCL-40-8BG400CES", "LIFCL-40-8BG400CES2", "LIFCL-40-8BG400C"]
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LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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LatticeNexusPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, mode="direct", prog="radiant"):
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assert mode in ["direct", "flash"]
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@ -11,7 +11,9 @@ import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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import litex_boards.platforms.antmicro_sdi_mipi_video_converter
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from litex.gen import LiteXModule
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from litex_boards.platforms import antmicro_sdi_mipi_video_converter
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from litex.soc.cores.ram import NXLRAM
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from litex.soc.cores.clock import NXPLL
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@ -23,33 +25,29 @@ from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.build.lattice.oxide import oxide_args, oxide_argdict
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from litex.build.lattice.radiant import radiant_build_argdict, radiant_build_args
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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# Built in OSC
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self.submodules.hf_clk = NXOSCA()
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self.hf_clk = NXOSCA()
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hf_clk_freq = 25e6
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self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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por_done = Signal()
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done)
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@ -59,72 +57,60 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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mem_map = {
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"rom": 0x00000000,
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"sram": 0x40000000,
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"main_ram": 0x60000000,
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"csr": 0xf0000000,
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"rom" : 0x00000000,
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"sram" : 0x40000000,
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"main_ram" : 0x60000000,
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"csr" : 0xf0000000,
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}
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def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs):
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platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform(
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device=device, toolchain=toolchain)
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def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant",
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with_led_chaser = True,
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**kwargs):
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platform = antmicro_sdi_mipi_video_converter.Platform(device=device, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore -----------------------------------------_----------------------------------------
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Antmicro SDI MIPI Video Converter Board", **kwargs)
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# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = NXLRAM(32, 64*kB)
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self.spram = NXLRAM(32, 64*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
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self.submodules.main_ram = NXLRAM(32, 64*kB)
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self.main_ram = NXLRAM(32, 64*kB)
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self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads=Cat(*[platform.request("user_led", i) for i in range(2)]),
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sys_clk_freq=sys_clk_freq)
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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builder_args(parser)
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soc_core_args(parser)
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oxide_args(parser)
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radiant_build_args(parser)
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=antmicro_sdi_mipi_video_converter.Platform, description="LiteX SoC on Antmicro SDI MIPI Video Converter Board.")
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parser.add_target_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=int(float(args.sys_clk_freq)),
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device=args.device,
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toolchain=args.toolchain,
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**soc_core_argdict(args)
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sys_clk_freq = int(float(args.sys_clk_freq)),
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device = args.device,
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toolchain = args.toolchain,
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**parser.soc_argdict
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else radiant_build_argdict(args)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**builder_kargs)
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target, args.programmer)
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