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Merge pull request #583 from hansfbaier/alientex_davincipro 

alientek davincipro: fix speedgrade
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enjoy-digital 2024-04-23 15:54:33 +02:00 committed by GitHub
parent a6b8457111 949debb3ca
commit 7cfc622353
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2 changed files with 3 additions and 3 deletions
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2
litex_boards/platforms/alientek_davincipro.py
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@ -314,7 +314,7 @@ class Platform(Xilinx7SeriesPlatform):
assert variant in ["a7-35", "a7-100"]
kgates = variant.split("-")[-1]
self.kgates = kgates
Xilinx7SeriesPlatform.__init__(self, f"xc7a{kgates}t-fgg484-1", _io, _connectors, toolchain=toolchain)
Xilinx7SeriesPlatform.__init__(self, f"xc7a{kgates}t-fgg484-2", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",

4
litex_boards/targets/alientek_davincipro.py
View File

@ -55,7 +55,7 @@ class _CRG(LiteXModule):
rst = ~platform.request("cpu_reset") if with_rst else 0
# PLL.
self.pll = pll = S7PLL(speedgrade=-1)
self.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(rst | self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
@ -71,7 +71,7 @@ class _CRG(LiteXModule):
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
if with_hdmi:
self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-1)
self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
self.comb += pll2.reset.eq(rst | self.rst)
pll2.register_clkin(clk50, 50e6)
pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)