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aller/nereid/tagus: update litepcie

This commit is contained in:
Florent Kermarrec 2020-01-21 21:26:23 +01:00
parent 684c1640bb
commit 8113b491db
3 changed files with 0 additions and 6 deletions
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2
litex_boards/partner/targets/aller.py
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@ -90,8 +90,6 @@ class PCIeSoC(SoCSDRAM):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# pcie phy # pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")

2
litex_boards/partner/targets/nereid.py
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@ -89,8 +89,6 @@ class PCIeSoC(SoCSDRAM):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# pcie phy # pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")

2
litex_boards/partner/targets/tagus.py
View File

@ -91,8 +91,6 @@ class PCIeSoC(SoCSDRAM):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# pcie phy # pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")